公开(公告)号：US07447946B2

公开(公告)日：2008-11-04

申请号：US10981741

申请日：2004-11-05

申请人： David F McHale ,  Rahoul K Varma ,  Marc R Wicks ,  Mike Livesley ,  Gareth Duncan

发明人： David F McHale ,  Rahoul K Varma ,  Marc R Wicks ,  Mike Livesley ,  Gareth Duncan

IPC分类号： G06F11/00

CPC分类号： G06F11/348

摘要： The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

摘要翻译： 本发明提供一种用于存储跟踪数据的数据处理装置和方法。 数据处理装置包括总线，其可操作以互连多个主设备和从设备，以使事务能够在主设备和从设备之间路由。 每个主设备能够启动事务，事务指定事务地址。 高速缓存插在至少一个主设备和总线之间，并且可操作以接收该主设备发出的交易。 高速缓存具有高速缓冲存储器和高速缓存控制器，其可操作以控制对高速缓冲存储器的访问。 高速缓存控制器包括缓存逻辑，其可操作以选择性地高速缓存在取决于交易地址选择的高速缓冲存储器中的位置处的事务的数据值。 提供控制存储器，标识指定跟踪区域的跟踪地址范围。 此外，提供跟踪逻辑，其可操作以选择性地生成作为跟踪数据的与事务相关联的一个或多个属性，并且与跟踪数据相关联地提供从跟踪地址范围中选择的跟踪地址。 然后，缓存逻辑可操作以将跟踪数据存储在根据跟踪地址选择的高速缓冲存储器中的位置。 以这种方式，可以以灵活的方式使用高速缓存，以便不仅用作正常高速缓存，而且可以选择性地存储在高速缓存跟踪数据内。