公开(公告)号：US07447946B2

公开(公告)日：2008-11-04

申请号：US10981741

申请日：2004-11-05

申请人： David F McHale ,  Rahoul K Varma ,  Marc R Wicks ,  Mike Livesley ,  Gareth Duncan

发明人： David F McHale ,  Rahoul K Varma ,  Marc R Wicks ,  Mike Livesley ,  Gareth Duncan

IPC分类号： G06F11/00

CPC分类号： G06F11/348

摘要： The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

摘要翻译： 本发明提供一种用于存储跟踪数据的数据处理装置和方法。 数据处理装置包括总线，其可操作以互连多个主设备和从设备，以使事务能够在主设备和从设备之间路由。 每个主设备能够启动事务，事务指定事务地址。 高速缓存插在至少一个主设备和总线之间，并且可操作以接收该主设备发出的交易。 高速缓存具有高速缓冲存储器和高速缓存控制器，其可操作以控制对高速缓冲存储器的访问。 高速缓存控制器包括缓存逻辑，其可操作以选择性地高速缓存在取决于交易地址选择的高速缓冲存储器中的位置处的事务的数据值。 提供控制存储器，标识指定跟踪区域的跟踪地址范围。 此外，提供跟踪逻辑，其可操作以选择性地生成作为跟踪数据的与事务相关联的一个或多个属性，并且与跟踪数据相关联地提供从跟踪地址范围中选择的跟踪地址。 然后，缓存逻辑可操作以将跟踪数据存储在根据跟踪地址选择的高速缓冲存储器中的位置。 以这种方式，可以以灵活的方式使用高速缓存，以便不仅用作正常高速缓存，而且可以选择性地存储在高速缓存跟踪数据内。

公开(公告)号：US07861095B2

公开(公告)日：2010-12-28

申请号：US11057373

申请日：2005-02-15

申请人： Rahoul Kumar Varma ,  Marc Richard Wicks ,  Gareth Duncan ,  David Francis McHale ,  Mike Livesley

发明人： Rahoul Kumar Varma ,  Marc Richard Wicks ,  Gareth Duncan ,  David Francis McHale ,  Mike Livesley

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F12/0897

摘要： A data processing apparatus is provided, which is operable to access data values associated with a respective address values. The data processing apparatus has: a processor; a main memory having a secure data values region; a cache; and cache interface logic having data transaction logic and security determination logic. The data transaction logic receives from the processor a data access request for accessing data in cache. The data access request has an associated address value and a security attribute. If the security attribute indicates that the request is a non-secure data-access request, the security determination logic determines, via a data region allocation table, whether the request is associated with the secure data values region of main memory and the non-secure data access request is allowed to complete if it is not associated with the secure data region.

摘要翻译： 提供了一种数据处理装置，其可操作以访问与相应地址值相关联的数据值。 数据处理装置具有：处理器; 具有安全数据值区域的主存储器; 缓存; 以及具有数据事务逻辑和安全确定逻辑的高速缓存接口逻辑。 数据事务逻辑从处理器接收用于访问缓存中的数据的数据访问请求。 数据访问请求具有关联的地址值和安全属性。 如果安全属性指示请求是非安全数据访问请求，则安全确定逻辑经由数据区域分配表确定该请求是否与主存储器的安全数据值区域相关联，并且非安全 如果数据访问请求不与安全数据区域相关联，则允许数据访问请求完成。

公开(公告)号：US20060112310A1

公开(公告)日：2006-05-25

申请号：US10981741

申请日：2004-11-05

申请人： David McHale ,  Rahoul Varma ,  Marc Wicks ,  Mike Livesley ,  Gareth Duncan

发明人： David McHale ,  Rahoul Varma ,  Marc Wicks ,  Mike Livesley ,  Gareth Duncan

IPC分类号： G06F11/00

CPC分类号： G06F11/348

摘要： The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

摘要翻译： 本发明提供一种用于存储跟踪数据的数据处理装置和方法。 数据处理装置包括总线，其可操作以互连多个主设备和从设备，以使事务能够在主设备和从设备之间路由。 每个主设备能够启动事务，事务指定事务地址。 高速缓存插在至少一个主设备和总线之间，并且可操作以接收该主设备发出的交易。 高速缓存具有缓存存储器和高速缓存控制器，其可操作以控制对高速缓冲存储器的访问。 高速缓存控制器包括缓存逻辑，其可操作以选择性地高速缓存在取决于交易地址选择的高速缓冲存储器中的位置处的事务的数据值。 提供控制存储器，标识指定跟踪区域的跟踪地址范围。 此外，提供跟踪逻辑，其可操作以选择性地生成作为跟踪数据的与事务相关联的一个或多个属性，并且与跟踪数据相关联地提供从跟踪地址范围中选择的跟踪地址。 然后，缓存逻辑可操作以将跟踪数据存储在根据跟踪地址选择的高速缓冲存储器中的位置。 以这种方式，可以以灵活的方式使用高速缓存，以便不仅用作正常高速缓存，而且可以选择性地存储在高速缓存跟踪数据内。

公开(公告)号：US20060184804A1

公开(公告)日：2006-08-17

申请号：US11057373

申请日：2005-02-15

申请人： Rahoul Varma ,  Marc Wicks ,  Gareth Duncan ,  David McHale ,  Mike Livesley

发明人： Rahoul Varma ,  Marc Wicks ,  Gareth Duncan ,  David McHale ,  Mike Livesley

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F12/0897

摘要： A data processing apparatus operable to access data values, each data value being associated with a respective address value is disclosed. The data processing apparatus comprises: a processor operable to process an instruction which causes a data access request; a main memory operable to store data values, said main memory having a region of secure data values; a cache operable to store previously accessed data values; and cache interface logic comprising: data transaction logic operable to receive a data access request from said processor requesting a data value be accessed in said cache, said data access request having an address value and a security attribute associated therewith; and security determination logic operable, in the event that said security attribute indicates a non-secure data access request, to determine whether said non-secure data access request is associated with said region of secure data values by interrogating a data region allocation table and, in the event that said data region allocation table provides an indication that said address value is not associated with said secure data region, to enable said data access request to complete. By determining whether the non-secure data access request is not associated with the region of secure data, it is possible to ensure that no non-secure data accesses occur for address values within a secure region.

摘要翻译： 公开了一种用于访问数据值的数据处理装置，每个数据值与相应的地址值相关联。 数据处理装置包括：处理器，可操作以处理引起数据访问请求的指令; 主存储器，用于存储数据值，所述主存储器具有安全数据值的区域; 用于存储先前访问的数据值的缓存; 以及高速缓存接口逻辑，包括：数据事务逻辑，可操作以从所述处理器接收请求在所述高速缓存中访问的数据值的数据访问请求，所述数据访问请求具有与之相关联的地址值和安全属性; 以及安全性确定逻辑，用于在所述安全属性指示非安全数据访问请求的情况下，通过询问数据区域分配表来确定所述非安全数据访问请求是否与所述安全数据值区域相关联， 在所述数据区域分配表提供所述地址值未与所述安全数据区域相关联的指示的情况下，使所述数据访问请求完成。 通过确定非安全数据访问请求是否与安全数据的区域相关联，可以确保对安全区域内的地址值不发生非安全数据访问。