Optimization of abutted-pin hierarchical physical design
    1.
    发明授权
    Optimization of abutted-pin hierarchical physical design 失效
    对接针层级物理设计优化

    公开(公告)号:US06857116B1

    公开(公告)日:2005-02-15

    申请号:US09714722

    申请日:2000-11-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 G06F17/5031

    摘要: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

    摘要翻译: 描述了一种对接的分层物理设计过程。 对接销分层物理设计为传统分层物理设计的问题提供了解决方案,并提供了附加的优点和优点。 特别地,对接针层级物理设计没有通道。 此外,在对接分层物理设计中,顶层的组件被合并到块级,使得顶级网表显着地减少。

    Method and system for implementing a graphical user interface for defining and linking multiple attach points for multiple blocks of an integrated circuit netlist
    2.
    发明授权
    Method and system for implementing a graphical user interface for defining and linking multiple attach points for multiple blocks of an integrated circuit netlist 有权
    用于实现用于定义和链接集成电路网表的多个块的多个附接点的图形用户界面的方法和系统

    公开(公告)号:US06564363B1

    公开(公告)日:2003-05-13

    申请号:US09909050

    申请日:2001-07-18

    IPC分类号: G06F9455

    CPC分类号: G06F17/5068

    摘要: A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file containing identifications of a plurality of blocks of cells of the integrated circuit netlist, each block representing circuit components to be realized in physical form. A view of the plurality blocks is presented to a user, the view provided by a computer display. Attach points are defined for each block. Connections for the blocks are defined by graphically linking the attach points of the respective blocks. The input file is updated in accordance with the defined connections.

    摘要翻译: 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法。 该方法包括访问包含集成电路网表的多个单元块的标识的输入文件,每个块表示将以物理形式实现的电路组件。 将多个块的视图呈现给用户,由计算机显示器提供的视图。 为每个块定义连接点。 块的连接通过图形地链接相应块的附着点来定义。 输入文件根据定义的连接进行更新。

    Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist
    3.
    发明授权
    Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist 有权
    用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法和系统

    公开(公告)号:US06557153B1

    公开(公告)日:2003-04-29

    申请号:US09714296

    申请日:2000-11-15

    IPC分类号: G06F9455

    CPC分类号: G06F17/5068

    摘要: A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing vertical and horizontal dimensions of an area of an integrated circuit netlist and accessing a grid for power and ground lines of the integrated circuit netlist. A view is presented of the grid to a user by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, wherein each block represents circuit components to be realized in physical form. The dimensions of the plurality of blocks to the grid such that the dimensions of the blocks align with the grid.

    摘要翻译: 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法。 该方法包括访问集成电路网表的区域的垂直和水平维度,并访问集成电路网表的电源和接地线的电网。 通过计算机显示器向用户呈现网格的视图。 访问集成电路网表的多个单元块,其中每个块表示将以物理形式实现的电路组件。 多个块到网格的尺寸使得块的尺寸与栅格对齐。

    Method and system for implementing a graphical user interface for depicting loose fly line interconnections between multiple blocks of an integrated circuit netlist
    4.
    发明授权
    Method and system for implementing a graphical user interface for depicting loose fly line interconnections between multiple blocks of an integrated circuit netlist 有权
    用于实现用于描绘集成电路网表的多个块之间的松散线路互连的图形用户界面的方法和系统

    公开(公告)号:US06553554B1

    公开(公告)日:2003-04-22

    申请号:US09908957

    申请日:2001-07-18

    IPC分类号: G06F9455

    CPC分类号: G06F17/5068

    摘要: A method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes the step of accessing vertical and horizontal dimensions of an area of an integrated circuit netlist. A grid for power and ground lines of the integrated circuit netlist is then accessed. A view of the grid is presented to a user, wherein the view is provided by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, with each block representing circuit components to be realized in physical form. The dimensions of the plurality of blocks are snapped to the grid such that the dimensions of the blocks align with the grid.

    摘要翻译: 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法和系统。 该方法包括访问集成电路网表的区域的垂直和水平维度的步骤。 然后访问集成电路网表的电源和接地线的电网。 网格的视图呈现给用户,其中视图由计算机显示器提供。 访问集成电路网表的多个单元块,每个块表示以物理形式实现的电路组件。 多个块的尺寸被卡扣到网格,使得块的尺寸与栅格对准。

    Optimization of the top level in abutted-pin hierarchical physical design
    5.
    发明授权
    Optimization of the top level in abutted-pin hierarchical physical design 失效
    对接针层次物理设计中顶级的优化

    公开(公告)号:US06865721B1

    公开(公告)日:2005-03-08

    申请号:US10104960

    申请日:2002-03-22

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 G06F17/5031

    摘要: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

    摘要翻译: 描述了一种对接的分层物理设计过程。 对接针层级物理设计为传统分层物理设计的问题提供了解决方案,并提供了额外的优点和优点。 特别地,对接针层级物理设计没有通道。 此外,在对接分层物理设计中,顶层的组件被合并到块级,使得顶级网表显着地减少。

    Facilitating press operation in abutted-pin hierarchical physical design
    6.
    发明授权
    Facilitating press operation in abutted-pin hierarchical physical design 失效
    便于按键分层物理设计的按压操作

    公开(公告)号:US06854093B1

    公开(公告)日:2005-02-08

    申请号:US10104813

    申请日:2002-03-22

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 G06F17/5031

    摘要: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

    摘要翻译: 描述了一种对接的分层物理设计过程。 对接针层级物理设计为传统分层物理设计的问题提供了解决方案,并提供了额外的优点和优点。 特别地,对接针层级物理设计没有通道。 此外,在对接分层物理设计中,顶层的组件被合并到块级,使得顶级网表显着地减少。

    Method and system for automatically generating low level program commands as dependency graphs from high level physical design stages
    7.
    发明授权
    Method and system for automatically generating low level program commands as dependency graphs from high level physical design stages 有权
    从高级物理设计阶段自动生成低级程序命令作为依赖图的方法和系统

    公开(公告)号:US06574788B1

    公开(公告)日:2003-06-03

    申请号:US09712418

    申请日:2000-11-13

    IPC分类号: G06F1750

    CPC分类号: G06F17/5068

    摘要: A method and system for automatically generating low level design tool commands as dependency graphs from abstracted high level physical design stages. The novel system inputs names of blocks of a hierarchical integrated circuit. Each block name has associated with it certain variables, stages and conditional statements. The stages represent a set of linked physical design processes that are to be executed on the block. Stages can be dependent on other stages and therefore are executed in-order on the block depending on how they are linked in the input set. The system automatically generates, from the input set, a dependency graph for each block. The dependency graph includes a large volume of nodes with associated parameters and options. Each node includes one or more low level program commands (“tasks”) for directing a number of physical design tools, e.g., programs, to perform various functions with respect to the block. Each node can receive input and generate an output. If the input to a particular node has not been altered, e.g., since the last time the graphs were executed, then that node is not executed in the current run. Dependency graphs that are not data dependent can be executed in parallel. If the input set is altered, a new set of dependency graphs can automatically be generated. By grouping the physical design operations into stages, the novel system allows the user to abstract the problem of dealing with large numbers of physical design tasks into the more manageable problem of dealing with high level “stages” in the physical design process.

    摘要翻译: 一种从抽象的高级物理设计阶段自动生成低级设计工具命令作为依赖图的方法和系统。 新颖的系统输入分层集成电路的块的名称。 每个块名称都与其相关联的某些变量,阶段和条件语句。 这些阶段表示要在块上执行的一组链接的物理设计过程。 阶段可以依赖于其他阶段,因此根据它们在输入集中的链接方式按顺序执行。 系统自动从输入集合生成每个块的依赖图。 依赖关系图包括具有相关参数和选项的大量节点。 每个节点包括一个或多个低级程序命令(“任务”),用于引导多个物理设计工具,例如程序,以执行关于块的各种功能。 每个节点可以接收输入并产生一个输出。 如果特定节点的输入没有被改变,例如,由于上次执行图形,那么该节点在当前的运行中不被执行。 不依赖于数据的依赖关系图可以并行执行。 如果输入集合被更改,则可以自动生成一组新的依赖关系图。 通过将物理设计操作分为几个阶段,新系统允许用户将处理大量物理设计任务的问题抽象为处理物理设计过程中高级“阶段”的更易于管理的问题。

    Facilitating verification in abutted-pin hierarchical physical design
    8.
    发明授权
    Facilitating verification in abutted-pin hierarchical physical design 失效
    促进验证在邻接针层级物理设计

    公开(公告)号:US06757874B1

    公开(公告)日:2004-06-29

    申请号:US10104786

    申请日:2002-03-22

    IPC分类号: G06F1750

    CPC分类号: G06F17/5068 G06F17/5031

    摘要: An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

    摘要翻译: 描述了一种对接的分层物理设计过程。 对接针层级物理设计为传统分层物理设计的问题提供了解决方案,并提供了额外的优点和优点。 特别地,对接针层级物理设计没有通道。 此外,在对接分层物理设计中,顶层的组件被合并到块级,使得顶级网表显着地减少。

    Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file
    9.
    发明授权
    Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file 有权
    使用主库文件和可修改的主库文件来维护集成电路网表的元素摘要的方法和系统

    公开(公告)号:US06564364B1

    公开(公告)日:2003-05-13

    申请号:US09909354

    申请日:2001-07-18

    IPC分类号: G06F9455

    CPC分类号: G06F17/5068

    摘要: A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file and parsing the input file to identify elements within the netlist matching corresponding elements within a first library file. At least one element within the netlist is identified that does not have a corresponding element within the first library file. A modifiable element corresponding to the at least one element is stored within a second library file. A subsequent occurrence of the at least one element is matched to the modifiable element in the second library file. The parsing of the input file of the integrated circuit netlist is completed and a build of the integrated circuit netlist is then completed based on the parsed input file and specifications stored in the first or second library files.

    摘要翻译: 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法。 该方法包括访问输入文件并解析输入文件以识别与第一库文件内的相应元素匹配的网表内的元素。 网表中至少有一个元素在第一个库文件中没有相应的元素。 对应于至少一个元素的可修改元素被存储在第二库文件中。 随后发生的至少一个元素与第二库文件中的可修改元素相匹配。 完成集成电路网表的输入文件的解析,然后基于解析的输入文件和存储在第一或第二库文件中的规范,完成集成电路网表的构建。