公开(公告)号：US20070136709A1

公开(公告)日：2007-06-14

申请号：US11608689

申请日：2006-12-08

申请人： Paul Rodman

发明人： Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

摘要翻译： 提供和描述了用于布局规划分层物理设计以改善布局和布线的方法。 在一个实施例中，布局规划分层物理设计的方法包括在分层物理设计的顶层布置多个块。 每个块包括多个线性边缘。 另外，选择至少一个块。 此外，所选块的至少一个线性边缘被光栅化。 该光栅化包括将线性边缘转换成阶梯形边缘。

公开(公告)号：US20050135242A1

公开(公告)日：2005-06-23

申请号：US10875995

申请日：2004-06-24

申请人： James Larsen ,  Paul Rodman

发明人： James Larsen ,  Paul Rodman

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04W40/02 ,  H04W40/10 ,  H04W40/24 ,  H04W84/04 ,  H04W84/22 ,  H04W88/04 ,  H04L12/26

CPC分类号： H04W40/24 ,  H04W24/00 ,  H04W40/02 ,  H04W40/10 ,  H04W40/246 ,  H04W74/00 ,  H04W84/042 ,  H04W84/22 ,  H04W88/04 ,  H04W88/08 ,  Y02D70/142 ,  Y02D70/30 ,  Y02D70/326

摘要： The invention relates to a method of operating a communication network, the network comprising a plurality of stations which are able to transmit data to and receive data from one another so that a message comprising a plurality of data packets is sent from an originating station to a destination station via at least one opportunistically selected intermediate station. The method makes use of probe signals transmitted from each station on a selected probing channel to which other stations respond to indicate their availability as destination or intermediate stations. A Request to Send message is sent, with a Clear to Send message returned by an available station. The station with data to send opportunistically selects an available station and the selected station uses a Packet Acknowledge message to confirm successful reception of the transmitted data packet. An End-to-End Acknowledge message is sent by the originating station, directly or indirectly, to confirm receipt of said data packets.

摘要翻译： 本发明涉及一种操作通信网络的方法，该网络包括能够将数据彼此传输和接收数据的多个站，使得包括多个数据分组的消息从始发站发送到 目的地站经由至少一个机会选择的中间站。 该方法利用从其他站响应的所选探测信道上的每个站发送的探测信号，以指示其作为目的地或中间站的可用性。 发送请求发送消息，具有由可用站返回的清除发送消息。 具有要发送的数据的站机会地选择可用站，并且所选站使用分组确认消息来确认成功接收所发送的数据分组。 端到端确认消息由发起站直接或间接地发送以确认接收到所述数据分组。

公开(公告)号：US06857116B1

公开(公告)日：2005-02-15

申请号：US09714722

申请日：2000-11-15

申请人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

发明人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

摘要翻译： 描述了一种对接的分层物理设计过程。 对接销分层物理设计为传统分层物理设计的问题提供了解决方案，并提供了附加的优点和优点。 特别地，对接针层级物理设计没有通道。 此外，在对接分层物理设计中，顶层的组件被合并到块级，使得顶级网表显着地减少。

公开(公告)号：US06564363B1

公开(公告)日：2003-05-13

申请号：US09909050

申请日：2001-07-18

申请人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

发明人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

IPC分类号： G06F9455

CPC分类号： G06F17/5068

摘要： A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file containing identifications of a plurality of blocks of cells of the integrated circuit netlist, each block representing circuit components to be realized in physical form. A view of the plurality blocks is presented to a user, the view provided by a computer display. Attach points are defined for each block. Connections for the blocks are defined by graphically linking the attach points of the respective blocks. The input file is updated in accordance with the defined connections.

摘要翻译： 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法。 该方法包括访问包含集成电路网表的多个单元块的标识的输入文件，每个块表示将以物理形式实现的电路组件。 将多个块的视图呈现给用户，由计算机显示器提供的视图。 为每个块定义连接点。 块的连接通过图形地链接相应块的附着点来定义。 输入文件根据定义的连接进行更新。

公开(公告)号：US06557153B1

公开(公告)日：2003-04-29

申请号：US09714296

申请日：2000-11-15

申请人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

发明人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

IPC分类号： G06F9455

CPC分类号： G06F17/5068

摘要： A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing vertical and horizontal dimensions of an area of an integrated circuit netlist and accessing a grid for power and ground lines of the integrated circuit netlist. A view is presented of the grid to a user by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, wherein each block represents circuit components to be realized in physical form. The dimensions of the plurality of blocks to the grid such that the dimensions of the blocks align with the grid.

摘要翻译： 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法。 该方法包括访问集成电路网表的区域的垂直和水平维度，并访问集成电路网表的电源和接地线的电网。 通过计算机显示器向用户呈现网格的视图。 访问集成电路网表的多个单元块，其中每个块表示将以物理形式实现的电路组件。 多个块到网格的尺寸使得块的尺寸与栅格对齐。

公开(公告)号：US06553554B1

公开(公告)日：2003-04-22

申请号：US09908957

申请日：2001-07-18

申请人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

发明人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

IPC分类号： G06F9455

CPC分类号： G06F17/5068

摘要： A method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes the step of accessing vertical and horizontal dimensions of an area of an integrated circuit netlist. A grid for power and ground lines of the integrated circuit netlist is then accessed. A view of the grid is presented to a user, wherein the view is provided by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, with each block representing circuit components to be realized in physical form. The dimensions of the plurality of blocks are snapped to the grid such that the dimensions of the blocks align with the grid.

摘要翻译： 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法和系统。 该方法包括访问集成电路网表的区域的垂直和水平维度的步骤。 然后访问集成电路网表的电源和接地线的电网。 网格的视图呈现给用户，其中视图由计算机显示器提供。 访问集成电路网表的多个单元块，每个块表示以物理形式实现的电路组件。 多个块的尺寸被卡扣到网格，使得块的尺寸与栅格对准。

公开(公告)号：US06247124B1

公开(公告)日：2001-06-12

申请号：US09363635

申请日：1999-07-30

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F932

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

摘要翻译： 计算系统包括具有存储多条指令的多行的指令存储器的装置，以及存储多个分支预测条目的分支存储器，每个分支预测条目包含用于预测分支指定的分支 存储在指令存储器中的指令将在执行分支指令时进行。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

公开(公告)号：US5510934A

公开(公告)日：1996-04-23

申请号：US168832

申请日：1993-12-15

申请人： John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang ,  Steve J. Ciavaglia

发明人： John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang ,  Steve J. Ciavaglia

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/0851

摘要： A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.

摘要翻译： 用于数据处理器的分级高速缓冲存储器系统包括单个芯片整数单元，诸如浮点单元的陆军处理器，外部主存储器和分割级高速缓存。 分级高速缓存包括片上快速本地高速缓存，具有低延迟，用于整数单元用于整数和地址数据的加载和存储，以及用于存储诸如浮点数据的数据阵列的片外流水线全局高速缓存 供数组处理器使用，整数和地址数据用于重新填充本地缓存。 通过在整数存储期间写入全局缓存来维护本地缓存和全局缓存之间的一致性。 在陆军处理器存储期间将数据写入全局缓存时，本地缓存字无效。

公开(公告)号：US07185305B1

公开(公告)日：2007-02-27

申请号：US10855539

申请日：2004-05-26

申请人： Paul Rodman

发明人： Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： Methods of creating a power distribution arrangement with tapered metal wires for a physical design are provided and described. In one embodiment, a method of creating a power distribution arrangement for a physical design of an integrated circuit includes arranging a plurality of metal wires for power distribution in a desired arrangement. Each metal wire has a width. Furthermore, the metal wires are tapered such that the width is thicker in a core edge area of the physical design than in a core center area of the physical design. In other embodiments, a method of creating a power distribution arrangement for a physical design of a current integrated circuit includes arranging a plurality of metal wires for power distribution in a desired arrangement. The metal wires are tapered using a routing congestion profile and/or a voltage drop profile of a prior physical design of a prior integrated circuit.

摘要翻译： 提供并描述了用于物理设计的用锥形金属线制造配电装置的方法。 在一个实施例中，创建用于集成电路的物理设计的配电装置的方法包括以期望的布置布置多个用于配电的金属线。 每个金属线具有宽度。 此外，金属线是锥形的，使得在物理设计的芯边缘区域中的宽度比在物理设计的核心中心区域更宽。 在其他实施例中，创建用于当前集成电路的物理设计的配电装置的方法包括以期望的布置布置多个用于配电的金属线。 使用现有集成电路的现有物理设计的路由拥塞分布和/或电压降分布图，金属线是锥形的。

公开(公告)号：US07155693B1

公开(公告)日：2006-12-26

申请号：US10831700

申请日：2004-04-23

申请人： Paul Rodman

发明人： Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

摘要翻译： 提供和描述了用于布局规划分层物理设计以改善布局和布线的方法。 在一个实施例中，布局规划分层物理设计的方法包括在分层物理设计的顶层布置多个块。 每个块包括多个线性边缘。 另外，选择至少一个块。 此外，所选块的至少一个线性边缘被光栅化。 该光栅化包括将线性边缘转换成阶梯形边缘。