公开(公告)号：US20090154251A1

公开(公告)日：2009-06-18

申请号：US11959122

申请日：2007-12-18

申请人： Gwyn Robert Jones ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Mark William Randolph

发明人： Gwyn Robert Jones ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Mark William Randolph

IPC分类号： G11C7/00

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2211/5621

摘要： Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.

摘要翻译： 提供了用于在存储器件的选定字线上精确编程或擦除一个或多个存储器单元的方法和系统。 在一个实施例中，存储器件包括存储器阵列，阈值电压测量部件，被配置为测量存储器阵列的选定字线上的每个存储器单元的阈值电压，以及平均阈值电压确定部件，被配置为确定平均阈值电压 结果与所选择的字线唯一地相关联，基于所测量的阈值电压。 存储器装置被配置为相对于所确定的平均阈值电压将一个或多个存储器单元编程到预定程序级，或者将所选字线的存储单元擦除到所确定的平均阈值电压。 该方法对于多级闪存单元特别有用，以减少电荷损耗，同时提高编程元件状态的数据可靠性和Vt分布。

公开(公告)号：US07619932B2

公开(公告)日：2009-11-17

申请号：US11959122

申请日：2007-12-18

申请人： Gwyn Robert Jones ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Mark William Randolph

发明人： Gwyn Robert Jones ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Mark William Randolph

IPC分类号： G11C11/34

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2211/5621

摘要： Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.

摘要翻译： 提供了用于在存储器件的选定字线上精确编程或擦除一个或多个存储器单元的方法和系统。 在一个实施例中，存储器件包括存储器阵列，阈值电压测量部件，被配置为测量存储器阵列的选定字线上的每个存储器单元的阈值电压，以及平均阈值电压确定部件，被配置为确定平均阈值电压 结果与所选择的字线唯一地相关联，基于所测量的阈值电压。 存储器装置被配置为相对于所确定的平均阈值电压将一个或多个存储器单元编程到预定程序级，或者将所选字线的存储单元擦除到所确定的平均阈值电压。 该方法对于多级闪存单元特别有用，以减少电荷损耗，同时提高编程元件状态的数据可靠性和Vt分布。

公开(公告)号：US07160773B2

公开(公告)日：2007-01-09

申请号：US10839614

申请日：2004-05-05

申请人： Mark William Randolph

发明人： Mark William Randolph

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11517 ,  H01L27/11568

摘要： Methods and structures are presented for protecting flash memory wordlines and memory cells from process-related charging during fabrication. Undoped polysilicon is formed at the ends of doped polysilicon wordlines to create resistors through which process charges are discharged to a doped polysilicon discharge structure coupled with a substrate. The wordlines, resistors, and the discharge structure can be formed as a unitary patterned polysilicon structure, where the wordline and discharge portions are selectively doped to be conductive and the resistor portions are substantially undoped to provide a resistance high enough to allow normal cell operation after fabrication while providing a discharge path for process-related charging during fabrication.

摘要翻译： 提出了用于在制造期间保护闪存字线和存储器单元免于与处理相关的充电的方法和结构。 在掺杂多晶硅字线的端部形成未掺杂的多晶硅，以产生电阻器，通过该电阻将工艺电荷放电到与衬底耦合的掺杂多晶硅放电结构。 字线，电阻器和放电结构可以形成为整体图案化多晶硅结构，其中字线和放电部分被选择性地掺杂为导电的，并且电阻器部分基本上未被掺杂以提供足够高的电阻以允许在 同时在制造期间提供用于处理相关充电的放电路径。

公开(公告)号：US06834012B1

公开(公告)日：2004-12-21

申请号：US10863673

申请日：2004-06-08

申请人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

发明人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.

摘要翻译： 提供了操作双位闪存器件和校正过擦除的双位闪存器件的方法。 本发明包括采用负栅极来校正过擦除的存储单元而没有基本上改变正确擦除的存储单元的阈值电压值或电荷状态的校正动作。 通过向栅极施加负栅极电压并将有源区域和衬底连接到地来执行负栅极应力作为块操作。