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    COMPOSITE IMPURITY SCHEME FOR MEMORY TECHNOLOGIES
    4.
    发明申请
    COMPOSITE IMPURITY SCHEME FOR MEMORY TECHNOLOGIES 有权
    内存技术的复合成本计划

    公开(公告)号：US20150279468A1

    公开(公告)日：2015-10-01

    申请号：US14242757

    申请日：2014-04-01

    申请人： Macronix International Co., Ltd.

    发明人： CHIH-WEI LEE ,  TIEN-FAN OU ,  JYUN-SIANG HUANG ,  CHIEN-HUNG LIU

    IPC分类号： G11C16/04 ,  H01L29/167 ,  H01L21/265 ,  G11C16/24 ,  H01L23/528 ,  H01L21/768 ,  H01L27/115 ,  G11C16/08

    CPC分类号： G11C16/0491 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L27/11568 ,  H01L29/1045 ,  H01L29/167

    摘要： An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

    摘要翻译： 集成电路包括存储器阵列，其包括在衬底中具有复合杂质分布的扩散位线。 多个字线覆盖在扩散位线之间的衬底中的通道区域，在交叉点处具有数据存储结构，例如浮置栅极结构或介电电荷俘获结构。 复合杂质扩散比特线在沟道区的相对侧上提供了具有高导电性，良好深度和陡峭掺杂分布的源极/漏极端子，即使沟道区临界尺寸低于50纳米。

    METHOD OF CONTROLLING MEMORY ARRAY
    5.
    发明申请
    METHOD OF CONTROLLING MEMORY ARRAY 审中-公开
    控制存储器阵列的方法

    公开(公告)号：US20150194217A1

    公开(公告)日：2015-07-09

    申请号：US14579368

    申请日：2014-12-22

    申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation

    发明人： Jing Gu ,  Yongfu Zhang

    IPC分类号： G11C16/14 ,  G11C16/26

    CPC分类号： G11C16/0491 ,  G11C16/0458

    摘要： A method of controlling a memory array is provided. The memory array includes memory cells, first control lines, second control lines, parallel bit lines and word lines that are perpendicular to the bit lines and are electrically insulated therefrom. The method includes selecting one or more of the memory cells and enabling a reading, a programming or an erasing operation on the selected memory cell(s) by applying different voltages respectively to word line(s), first control line(s) and second control line(s), connected to the selected memory cell(s), bit line(s) connected to source(s) of the selected memory cell(s) and bit line(s) connected to drain(s) of the selected memory cell(s), wherein the remaining one(s) of the first and second control line(s) that are connected to the unselected one(s) of the memory cell(s), is applied with a minus voltage ranging from −3 V to −0.5 V.

    摘要翻译： 提供了一种控制存储器阵列的方法。 存储器阵列包括垂直于位线并与其电绝缘的存储器单元，第一控制线，第二控制线，并行位线和字线。 该方法包括：通过将不同的电压分别施加到字线，第一控制线和第二控制线上，选择一个或多个存储器单元并使能对所选存储单元进行读取，编程或擦除操作 连接到所选择的存储器单元的控制线，连接到所选存储单元的源极的位线和连接到所选择的存储单元的漏极的位线 存储单元，其中连接到存储单元的未选择的一个或多个第一和第二控制线的剩余的一个或多个存储单元被施加负电压， 3 V至-0.5 V.

    Semiconductor device and method of controlling the same
    6.
    发明授权
    Semiconductor device and method of controlling the same 有权
    半导体装置及其控制方法

    公开(公告)号：US08787089B2

    公开(公告)日：2014-07-22

    申请号：US13692736

    申请日：2012-12-03

    申请人： Spansion LLC

    发明人： Masaru Yano ,  Kazuhide Kurosaki ,  Mototada Sakashita

    IPC分类号： G11C16/04 ,  G11C5/06 ,  G11C7/00 ,  G11C5/02 ,  G11C16/24 ,  G11C7/18

    CPC分类号： G11C16/0483 ,  G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0491 ,  G11C16/24 ,  G11C16/30

    摘要： An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.

    摘要翻译： 本发明的实施例提供一种半导体器件，其包括：包括非易失性存储器单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。 在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。 本发明的一个实施例还提供了一种控制半导体器件的方法。

    Parallel bitline nonvolatile memory employing channel-based processing technology
    7.
    发明授权
    Parallel bitline nonvolatile memory employing channel-based processing technology 有权
    并行位线非易失性存储器采用基于通道的处理技术

    公开(公告)号：US08681558B2

    公开(公告)日：2014-03-25

    申请号：US12575137

    申请日：2009-10-07

    申请人： Hagop Nazarian ,  Richard Fastow

    发明人： Hagop Nazarian ,  Richard Fastow

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

    摘要： Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

    摘要翻译： 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

    STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME
    8.
    发明申请
    STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME 有权
    带有选择门的存储器单元的行，包含这样的行的存储器件及其访问和形成方法

    公开(公告)号：US20130272066A1

    公开(公告)日：2013-10-17

    申请号：US13892353

    申请日：2013-05-13

    申请人： Micron Technology, Inc.

    发明人： Zengtao Liu

    IPC分类号： H01L27/115 ,  H01L29/66 ,  G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11517 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    摘要： Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

    摘要翻译： 具有字符串选择栅的存储单元串被配置成同时选择性地将字符串的端部耦合到数据线和源极线，提供包含这种字符串的存储器件以及用于访问和形成这种字符串的方法。 例如，公开了利用串行连接的非易失性存储器单元的垂直结构NAND串的非易失性存储器件。 一种这样的串包括两个或多个串联的非易失性存储单元，其中串的每一端与串的另一端共享串选择门。

    SILICON ON INSULATOR AND THIN FILM TRANSISTOR BANDGAP ENGINEERED SPLIT GATE MEMORY
    9.
    发明申请
    SILICON ON INSULATOR AND THIN FILM TRANSISTOR BANDGAP ENGINEERED SPLIT GATE MEMORY 有权
    绝缘子和薄膜晶体管上的绝缘子工程分割栅存储器

    公开(公告)号：US20130258784A1

    公开(公告)日：2013-10-03

    申请号：US13899629

    申请日：2013-05-22

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Hang-Ting Lue ,  Erh-Kun Lai

    IPC分类号： H01L29/66 ,  G11C16/04

    CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

    摘要： Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

    摘要翻译： 存储单元包括薄膜晶体管，堆叠阵列，采用无接合的NAND配置的带隙工程隧道层。 单元包括在绝缘层上形成的半导体条中的沟道区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括多层结构，所述多层结构包括至少一层，所述层具有低于与所述沟道区的界面处的空穴 - 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅电极描述了阵列和操作方法。

    ACCESSING AN NROM ARRAY
    10.
    发明申请
    ACCESSING AN NROM ARRAY 有权
    访问NROM阵列

    公开(公告)号：US20130223144A1

    公开(公告)日：2013-08-29

    申请号：US13845739

    申请日：2013-03-18

    申请人： Spansion Israel Ltd

    发明人： Eduardo MAAYAN

    IPC分类号： G11C16/10 ,  G11C16/30

    CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/30

    摘要： A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

    摘要翻译： 一种方法包括最小化在NROM存储器单元访问期间通过虚拟接地管泄漏的电流。 最小化包括大致一起操作两个相邻存储器单元，其包括将操作电压连接到两个相邻存储器单元的共享局部位线，并将两个相邻存储器单元的外部局部位线连接到接收单元，例如接地 电源或两个读出放大器。 还包括执行该方法的数组。