公开(公告)号：US08879733B2

公开(公告)日：2014-11-04

申请号：US13545564

申请日：2012-07-10

申请人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail

发明人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail

IPC分类号： G06F21/00 ,  H04L9/22 ,  G06F7/58

CPC分类号： H04L9/0869 ,  G06F7/582 ,  H04L9/0668

摘要： A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.

摘要翻译： 随机比特流生成器包括用于存储随机比特流生成器的当前内部状态的内部状态存储器和被配置为提供周期性比特序列的周期性比特序列生成器。 输出功能接收周期性位序列的位序列部分和当前内部状态的第一内部状态部分。 通过输出功能，基于比特序列部分和第一内部状态部分的布尔组合来确定随机比特流的新输出比特。 反馈装置通过执行涉及当前内部状态的新输出位和第二内部状态部分的布尔组合来将新的输出位馈送回内部状态存储器，以确定随机位产生器的下一个内部状态。

公开(公告)号：US20140019502A1

公开(公告)日：2014-01-16

申请号：US13545587

申请日：2012-07-10

申请人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail ,  Wieland Fischer

发明人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail ,  Wieland Fischer

IPC分类号： G06F7/58

CPC分类号： H04L9/0662 ,  G06F7/58 ,  H04L9/0668

摘要： A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.

摘要翻译： 随机比特流生成器包括多个反馈移位寄存器，其被配置为存储表示随机比特流生成器的内部状态的多个比特值。 每个反馈移位寄存器包括寄存器输入和寄存器输出。 随机比特流生成器还包括布尔输出功能，其被配置为从多个反馈寄存器接收多个寄存器输出，以执行多个寄存器输出的第一布尔组合，并提供相应的输出位，其中多个 的连续输出位形成随机比特流。 反馈回路被配置为执行输出位与至少一个反馈移位寄存器的至少一个寄存器反馈位的第二布尔组合，使得至少一个反馈移位寄存器的寄存器输入是 输出位。

公开(公告)号：US20140016778A1

公开(公告)日：2014-01-16

申请号：US13545564

申请日：2012-07-10

申请人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail

发明人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail

IPC分类号： H04L9/28

CPC分类号： H04L9/0869 ,  G06F7/582 ,  H04L9/0668

摘要： A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.

摘要翻译： 随机比特流生成器包括用于存储随机比特流生成器的当前内部状态的内部状态存储器和被配置为提供周期性比特序列的周期性比特序列生成器。 输出功能接收周期性位序列的位序列部分和当前内部状态的第一内部状态部分。 通过输出功能，基于比特序列部分和第一内部状态部分的布尔组合来确定随机比特流的新输出比特。 反馈装置通过执行涉及当前内部状态的新输出位和第二内部状态部分的布尔组合来将新的输出位馈送回内部状态存储器，以确定随机位产生器的下一个内部状态。

公开(公告)号：US20050182990A1

公开(公告)日：2005-08-18

申请号：US11070843

申请日：2005-02-24

申请人： Markus Gail ,  Jan Otterstedt

发明人： Markus Gail ,  Jan Otterstedt

IPC分类号： G06F11/00 ,  G06F21/00

CPC分类号： G06F21/71 ,  G06F9/321 ,  G06F9/3861 ,  G06F21/52 ,  G06F21/77

摘要： Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.

摘要翻译： 具有执行单元的数据处理装置，具有程序计数器的流量控制器和程序计数器传感器，其连接到数据总线和程序计数器。 程序计数器传感器具有逻辑单元，该逻辑单元确定下一个将经由数据总线传送的数据执行的指令的地址;以及比较器，其将确定的地址与程序计数器的内容进行比较，并触发报警信号 如果有任何差异。

公开(公告)号：US08861725B2

公开(公告)日：2014-10-14

申请号：US13545587

申请日：2012-07-10

申请人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail ,  Wieland Fischer

发明人： Rainer Goettfert ,  Berndt Gammel ,  Markus Gail ,  Wieland Fischer

IPC分类号： H04L9/22 ,  H04L9/06

CPC分类号： H04L9/0662 ,  G06F7/58 ,  H04L9/0668

摘要： A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.

摘要翻译： 随机比特流生成器包括多个反馈移位寄存器，其被配置为存储表示随机比特流生成器的内部状态的多个比特值。 每个反馈移位寄存器包括寄存器输入和寄存器输出。 随机比特流生成器还包括布尔输出功能，其被配置为从多个反馈寄存器接收多个寄存器输出，以执行多个寄存器输出的第一布尔组合，并提供相应的输出位，其中多个 的连续输出位形成随机比特流。 反馈回路被配置为执行输出位与至少一个反馈移位寄存器的至少一个寄存器反馈位的第二布尔组合，使得至少一个反馈移位寄存器的寄存器输入是 输出位。

公开(公告)号：US06708890B2

公开(公告)日：2004-03-23

申请号：US09821855

申请日：2001-03-30

申请人： Markus Gail ,  Wolfgang Pockrandt ,  Armin Wedel ,  Erwin Hess

发明人： Markus Gail ,  Wolfgang Pockrandt ,  Armin Wedel ,  Erwin Hess

IPC分类号： G06K1906

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G07F7/082 ,  G11C16/102

摘要： A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile, electrically writable and erasable flag memory, which is connected through an address line, a programming line and an authentication line to the assigned memory area, a programming voltage source and a data verification circuit. In the event of an alteration in the content of a memory area, the state of the associated flag memory is changed and, after verification of the programmed memory area content, the flag memory is returned to its basic state.

摘要翻译： 电路配置包括至少一个非易失性，电可擦除和可写入的存储区域。 每个存储器区域被分配有非易失性，电可写和可擦除标志存储器，其通过地址线，编程线和认证线连接到分配的存储区，编程电压源和数据验证电路。 在存储区域的内容发生变化的情况下，改变相关标志存储器的状态，并且在验证编程的存储器区域内容之后，标志存储器返回到其基本状态。

公开(公告)号：US20100182147A1

公开(公告)日：2010-07-22

申请号：US12356339

申请日：2009-01-20

申请人： Stefan Rueping ,  Thomas Nirschl ,  Ronald Kakoschke ,  Franz Josef Bruecklmayr ,  Markus Gail ,  Berndt Gammel ,  Gerd Dirscherl

发明人： Stefan Rueping ,  Thomas Nirschl ,  Ronald Kakoschke ,  Franz Josef Bruecklmayr ,  Markus Gail ,  Berndt Gammel ,  Gerd Dirscherl

IPC分类号： G08B13/00

CPC分类号： G06F21/86 ,  G11C13/0004 ,  G11C16/22

摘要： A security circuit comprising including a sensor located remotely from a central alarm handler and configured to sense an attack, and a phase-change memory cell coupled to and located remotely with the sensor, and configured to store an alarm event when the attack is sensed.

摘要翻译： 一种安全电路，包括：远离中央警报处理器并且被配置为感测攻击的传感器，以及耦合到所述传感器并远程位于所述传感器的位置存储器单元，并且被配置为在感测到所述攻击时存储警报事件。

公开(公告)号：US07634640B2

公开(公告)日：2009-12-15

申请号：US11070843

申请日：2005-02-24

申请人： Markus Gail ,  Jan Otterstedt

发明人： Markus Gail ,  Jan Otterstedt

IPC分类号： G06F9/44

CPC分类号： G06F21/71 ,  G06F9/321 ,  G06F9/3861 ,  G06F21/52 ,  G06F21/77

摘要： Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.

摘要翻译： 具有执行单元的数据处理装置，具有程序计数器的流量控制器和程序计数器传感器，其连接到数据总线和程序计数器。 程序计数器传感器具有逻辑单元，该逻辑单元确定下一个将经由数据总线传送的数据执行的指令的地址;以及比较器，其将确定的地址与程序计数器的内容进行比较，并触发报警信号 如果有任何差异。