公开(公告)号：US5239651A

公开(公告)日：1993-08-24

申请号：US815499

申请日：1991-12-30

申请人： Martin Sodos

发明人： Martin Sodos

IPC分类号： G06F13/28 ,  G06F13/30 ,  G06F13/362 ,  G06F15/167

CPC分类号： G06F13/30

摘要： A method and apparatus for arbitrating among multiple requested data transfers based on the availability of transfer resources. A request for the control of a resource is transmitted to an arbiter with information regarding the size of data transfer, internal buses and external buses required. The arbiter compares the information with the space remaining in the buffer, internal bus availability and external bus availability. If all the resources are available to complete the request, then the request is granted arbitration and the requested transfer is started. If any of the resources is not available, the arbiter takes the next request for evaluation. A mechanism is also provided for each request to require the arbiter to wait until all the resources are available to prevent the arbiter from taking on the next request.

公开(公告)号：US5367639A

公开(公告)日：1994-11-22

申请号：US815802

申请日：1991-12-30

申请人： Martin Sodos

发明人： Martin Sodos

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： An apparatus and method for performing direct memory access (DMA) to input/output (I/O) devices are described. In order to overcome storage limitations of a DMA controller, channel control blocks (CCBs) are stored in external memory. The DMA controller is programmed to reference a particular address of the external memory when a predetermined bit, referred to as a chain bit, in a current channel control block is set. The DMA controller will then perform a memory read operation on that area of memory and store a retrieved channel control block at a location previously utilized by an earlier channel control block. This process will continue until the chain bit is reset, at which time a DMA operation is complete. Dynamic chaining is easily accommodated whereby channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. The apparatus and method may be used to implement dynamic chaining without incurring race conditions. A wait bit is provided in each channel control block and, when this bit is set, the DMA controller will suspend operations thereby providing an opportunity for updating a chain of CCBs without incurring errors due to race conditions. Once the chain has been modified, the wait bit is reset and processing safely continues.

摘要翻译： 描述了用于对输入/输出（I / O）设备执行直接存储器存取（DMA）的设备和方法。 为了克服DMA控制器的存储限制，通道控制块（CCB）存储在外部存储器中。 当设定当前通道控制块中的称为链位的预定位时，DMA控制器被编程为引用外部存储器的特定地址。 然后，DMA控制器将对存储器的该区域执行存储器读取操作，并将检索到的通道控制块存储在先前通道控制块先前利用的位置。 此过程将一直持续到链条位复位，此时DMA操作完成。 易于容纳动态链接，从而在DMA访问期间可以动态地改变通道控制块以提供灵活的I / O系统。 该装置和方法可用于实现动态链接而不产生竞争条件。 在每个通道控制块中提供一个等待位，并且当该位被置位时，DMA控制器将暂停操作，从而提供更新CCB链的机会，而不会由于竞争条件而导致错误。 一旦链条被修改，等待位被重置并且安全地继续处理。

公开(公告)号：US5251312A

公开(公告)日：1993-10-05

申请号：US814864

申请日：1991-12-30

申请人： Martin Sodos

发明人： Martin Sodos

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/126 ,  G06F13/28

摘要： In the system of the present invention, the limitations imposed by the physical limitations of the DMA controller are overcome by storing the channel control blocks in external memory. The DMA controller is programmed to reference a particular address of external memory when a predetermined bit in the current channel control block is set. The DMA controller will then perform a memory read operation on the area of memory referred to by that address in order to store the retrieved channel control block at a location previously utilized by a earlier channel control block. This reading process will continue until the bit is reset, at which time the DMA operation is complete. Dynamic chaining is accommodated whereby the channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. Furthermore, a method and apparatus for implementing dynamic chaining without incurring race conditions is described. A wait bit in each channel control block is provided when this bit is set, the DMA controller will suspend operations thereby providing opportunity for updating the chain of CCBs without incurring errors due to race conditions. Once the chain has been modified, the wait bit is reset and processing safely continues.

摘要翻译： 在本发明的系统中，通过将通道控制块存储在外部存储器中来克服DMA控制器的物理限制所施加的限制。 当设置当前通道控制块中的预定位时，DMA控制器被编程为引用外部存储器的特定地址。 然后，DMA控制器将对由该地址引用的存储器区域执行存储器读取操作，以便将检索的信道控制块存储在先前通道控制块先前利用的位置。 该读取过程将持续到该位复位，此时DMA操作完成。 容纳动态链接，从而可以在DMA访问期间动态地改变信道控制块以提供灵活的I / O系统。 此外，描述了用于实现动态链接而不产生竞争条件的方法和装置。 当设置该位时，提供每个通道控制块中的等待位，DMA控制器将暂停操作，从而提供更新CCB链的机会，而不会由于竞争条件而导致错误。 一旦链条被修改，等待位被重置并且安全地继续处理。

公开(公告)号：US06754776B2

公开(公告)日：2004-06-22

申请号：US09861258

申请日：2001-05-17

申请人： Patrick N. Conway ,  Kazunori Masuyama ,  Takeshi Shimizu ,  Toshio Ogawa ,  Martin Sodos ,  Sudheer Miryala ,  Jeremy Farrell

发明人： Patrick N. Conway ,  Kazunori Masuyama ,  Takeshi Shimizu ,  Toshio Ogawa ,  Martin Sodos ,  Sudheer Miryala ,  Jeremy Farrell

IPC分类号： G06F1200

CPC分类号： G06F12/084 ,  G06F12/0813

摘要： A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.

摘要翻译： 公开了在计算机域之间逻辑分区共享存储器结构的系统和方法。 在一个实施例中，为每个域分配唯一的地址空间标识符。 唯一地址空间标识符优选地具有标签扩展和索引扩展位。 这允许使用标签扩展和索引扩展位来扩展常规本地域地址的标签和索引位。 可以使用扩展索引值来访问共享存储器结构中的数据条目。 命中可以使用扩展标签值来确定。

公开(公告)号：US5388237A

公开(公告)日：1995-02-07

申请号：US814766

申请日：1991-12-30

申请人： Martin Sodos

发明人： Martin Sodos

IPC分类号： G06F13/28 ,  G06F13/18

CPC分类号： G06F13/28

摘要： A method and apparatus for supporting multiple DMA channels by splitting data transfers for each channel into sequences of data slices and interleaving on a slice-by-slice basis. While the control of transfer resources may be shifted among the DMA channels, the ordering of the data slices for each channel is preserved. The present invention also discloses a circuit architecture capable of supporting the multiple interleaving DMA channels. The circuit architecture comprises a dual-port memory, channel sequencer, and channel interleave control. The dual-port memory stores slices of data to be transferred through the channels. A channel sequencer maintains the channel ordering of data slices in the dual-port memory. A channel interleave control unit allows channels to interleave their data transfers by monitoring the channel interleave size, current data transfer count and total transfer count per channel. A second channel is allowed to transfer data through the same medium as a first channel either when the first channel has reached its channel interleave size, or when the first channel has transferred its requested total transfer count, thus providing efficient bus utilization.

摘要翻译： 一种用于通过将每个信道的数据传输分割成数据片段和逐个片段的交织来支持多个DMA信道的方法和装置。 虽然传输资源的控制可能在DMA通道之间移动，但是每个通道的数据切片的顺序都被保留。 本发明还公开了一种能支持多交错DMA通道的电路架构。 电路架构包括双端口存储器，信道定序器和信道交织控制。 双端口存储器存储要通过通道传送的数据片段。 信道序列器维护双端口存储器中的数据片段的信道排序。 信道交织控制单元允许信道通过监视信道交织大小，当前数据传输计数和每个信道的总传输计数来交织其数据传输。 当第一信道已经达到其信道交织大小时，或者当第一信道已经转移其请求的总传输计数时，允许第二信道通过与第一信道相同的介质传送数据，从而提供有效的总线利用率。

公开(公告)号：US5386532A

公开(公告)日：1995-01-31

申请号：US814765

申请日：1991-12-30

申请人： Martin Sodos

发明人： Martin Sodos

IPC分类号： G06F5/06 ,  G06F5/10 ,  G06F13/28 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F5/065 ,  G06F13/28

摘要： A method and apparatus for supporting multiple DMA channels by splitting data transfers for each channel into sequences of data slices and interleaving on a slice-by-slice basis. While the control of transfer resources may be shifted among the DMA channels, the ordering of the data slices for each channel is preserved. The present invention also discloses a circuit architecture capable of supporting the multiple interleaving DMA channels. The circuit architecture comprises a dual-port memory, channel sequencer, and channel interleave control. The dual-port memory stores slices of data to be transferred through the channels. A channel sequencer maintains the channel ordering of data slices in the dual-port memory. A channel interleave control unit allows channels to interleave their data transfers by monitoring the channel interleave size, current data transfer count and total transfer count per channel. A second channel is allowed to transfer data through the same medium as a first channel either when the first channel has reached its channel interleave size, or when the first channel has transferred its requested total transfer count, thus providing efficient bus utilization.

摘要翻译： 一种用于通过将每个信道的数据传输分割成数据片段和逐个片段的交织来支持多个DMA信道的方法和装置。 虽然传输资源的控制可能在DMA通道之间移动，但是每个通道的数据切片的顺序都被保留。 本发明还公开了一种能够支持多交错DMA通道的电路架构。 电路架构包括双端口存储器，信道定序器和信道交织控制。 双端口存储器存储要通过通道传送的数据片段。 信道序列器维护双端口存储器中的数据片段的频道排序。 信道交织控制单元允许信道通过监视信道交织大小，当前数据传输计数和每个信道的总传输计数来交织其数据传输。 当第一信道已经达到其信道交织大小时，或者当第一信道已经转移其请求的总传输计数时，允许第二信道通过与第一信道相同的介质传送数据，从而提供有效的总线利用率。

公开(公告)号：US5280623A

公开(公告)日：1994-01-18

申请号：US846001

申请日：1992-03-04

申请人： Martin Sodos ,  Thomas Chan

发明人： Martin Sodos ,  Thomas Chan

IPC分类号： G06F13/36 ,  G06F13/28 ,  G06F13/42 ,  G06F13/362

CPC分类号： G06F13/28

摘要： An improved computer system bus is disclosed that transitions between addressed data transfers and handshake data transfers on the fly and that performs burst within dynamic data sizing during a data transfer sequence without prematurely terminating the sequence and that changes between synchronous and asynchronous data transfer sequences on the fly. These capabilities are accomplished by modifying the function of bus signal lines depending upon the type of transfer sequence undertaken. On the fly transition between addressed data transfer and handshake data transfer is accomplished by providing a set of DMA acknowledge signals and modifying their function according to the type of data transfer sequence underway. Burst within dynamic data sizing during a sequence is performed by taking advantage of burst transfer capabilities of the slave device, and the capability of the master device to modify data width on the fly. If the slave supports burst transfer, the bus master proceeds with a burst transfer sequence for the remaining portions of the data while shifting the data to accommodate the data width limitation of the slave device. On the fly transition between a synchronous transfer sequence and an asynchronous transfer sequence is accomplished by modifying the timing of bus acknowledge signals.

摘要翻译： 公开了一种改进的计算机系统总线，即在数据传输序列期间在寻址数据传输和握手数据传输之间进行转换，并且在数据传输序列期间在动态数​​据大小调整中执行突发，而不会过早地终止序列，并且在同步和异步数据传输序列之间进行改变 飞。 这些功能通过根据所进行的传输顺序的类型修改总线信号线的功能来实现。 寻址数据传输和握手数据传输之间的飞越转换是通过提供一组DMA确认信号并根据正在进行的数据传输序列的类型来修改其功能而实现的。 通过利用从设备的突发传送能力以及主设备在运行中修改数据宽度的能力来执行序列期间的动态数据大小中的突发。 如果从站支持突发传输，则总线主机在数据移动期间继续进行数据的剩余部分的突发传送序列，以适应从设备的数据宽度限制。 在同步传输序列和异步传输序列之间的飞越转换通过修改总线确认信号的时序来实现。