公开(公告)号：US06824201B2

公开(公告)日：2004-11-30

申请号：US10620355

申请日：2003-07-17

申请人： Masahide Miyazaki

发明人： Masahide Miyazaki

IPC分类号： B60R1300

CPC分类号： B60R13/025 ,  B60R13/0206 ,  B62D25/04

摘要： A pillar trim structure comprises: a vehicular pillar; a pillar trim for covering the pillar from the inner side of a compartment; a first retained member having its one end fixed on a vehicular widthwise face of the pillar trim and extended to the side of the pillar and its other end retained in a first hole formed in the pillar; and a second retained member having its one end fixed on the vehicular widthwise face of the pillar trim and extended to the side of the pillar and its other end retained in a second hole formed in the pillar. The engagements between the first and the second retained members, and the pillar can be released by deforming the pillar trim to separate the other end of the first retained member and the other end of the second retained member.

摘要翻译： 柱装饰结构包括：车柱; 用于从隔室的内侧覆盖支柱的支柱装饰件; 第一保持构件，其一端固定在柱装饰件的车宽横向面上并且延伸到柱的侧面，并且其另一端保持在形成在柱中的第一孔中; 以及第二保持构件，其一端固定在柱装饰件的车宽横向面上并延伸到柱的一侧，并且其另一端保持在形成在柱中的第二孔中。 第一和第二保持构件和支柱之间的接合可以通过使柱子装饰件变形而释放，以将第一保持构件的另一端和第二保持构件的另一端分开。

公开(公告)号：US06640198B2

公开(公告)日：2003-10-28

申请号：US09941754

申请日：2001-08-30

申请人： Masahide Miyazaki ,  Kazumi Hatayama ,  Kazunori Hikone ,  Seiji Kobayashi

发明人： Masahide Miyazaki ,  Kazumi Hatayama ,  Kazunori Hikone ,  Seiji Kobayashi

IPC分类号： G06F1125

CPC分类号： G11C29/16

摘要： The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.

摘要翻译： 本发明涉及根据存储在片上存储器中的测试程序使用其内置测试功能进行自检的LSI。 本发明的目的是在分支到片上存储器的地址空间中的地址发生的情况下有效地执行自检。程序计数器101存储存储器117和外部存储器的地址。 测试程序计数器108存储存储器117的地址。在测试模式中，程序计数器切换部109执行控制，使得当在程序计数器101中检测到存储器117的地址时，程序计数器的地址值 101，而当在程序计数器101中检测到外部存储器的地址时，选择测试程序计数器108的地址值。 签名压缩电路110签名压缩并保持程序计数器101的输出值。