公开(公告)号：US6032280A

公开(公告)日：2000-02-29

申请号：US847592

申请日：1997-04-24

申请人： Kazunori Hikone ,  Kazumi Hatayama ,  Takao Nishida ,  Hiromichi Yamada

发明人： Kazunori Hikone ,  Kazumi Hatayama ,  Takao Nishida ,  Hiromichi Yamada

摘要： An apparatus for producing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed. The apparatus also has an instruction sequence producing part for producing an instruction sequence in a machine language for the processor LSI by which an output from the block edge of the functional block becomes detectable at an external terminal of the processor LSI.

公开(公告)号：US07190593B2

公开(公告)日：2007-03-13

申请号：US10022732

申请日：2001-12-20

申请人： Kiyoshi Aiki ,  Kazunori Hikone ,  Hiroyuki Adachi ,  Masayoshi Okamoto ,  Masao Onose ,  Yuji Mizuno

发明人： Kiyoshi Aiki ,  Kazunori Hikone ,  Hiroyuki Adachi ,  Masayoshi Okamoto ,  Masao Onose ,  Yuji Mizuno

IPC分类号： H05K7/10 ,  H05K7/12

CPC分类号： H01L22/32 ,  G01R31/2884 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device. While the bonding pads along the pair of opposite sides of the semiconductor integrated circuit device are connected with leads along the four sides of the package, and some leads are bent toward the respective pads. The present invention the inspection of a plurality of semiconductor integrated circuit devices with probe needles at a time.

摘要翻译： 提供了一种半导体集成电路器件，其中（i）检查焊盘沿着半导体集成电路器件的一侧或两个相对侧布置，用于沿着除了侧面或两个相对侧之外的侧面布置的焊盘，以及（ii） 接合焊盘通过连接线连接到它们各自的检查焊盘。通过将探针施加到仅沿着半导体集成电路器件的一侧或两个相对侧布置的焊盘（检查焊盘和焊盘）来进行检查。 本发明还提供了一种半导体集成电路封装，其四边具有引线，包括具有沿四个侧面的一对相对侧布置的接合焊盘的半导体集成电路器件，以及用于支撑半导体集成电路器件的工作台。 虽然沿着半导体集成电路器件的这对相对侧的接合焊盘沿着封装的四边与引线连接，并且一些引线朝着相应的焊盘弯曲。 本发明一次检测具有探针的多个半导体集成电路器件。

公开(公告)号：US07036060B2

公开(公告)日：2006-04-25

申请号：US10452195

申请日：2003-06-03

申请人： Michinobu Nakao ,  Ryo Yamagata ,  Kazumi Hatayama ,  Seiji Kobayashi ,  Kazunori Hikone ,  Kotaro Shimamura

发明人： Michinobu Nakao ,  Ryo Yamagata ,  Kazumi Hatayama ,  Seiji Kobayashi ,  Kazunori Hikone ,  Kotaro Shimamura

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

公开(公告)号：US06640198B2

公开(公告)日：2003-10-28

申请号：US09941754

申请日：2001-08-30

申请人： Masahide Miyazaki ,  Kazumi Hatayama ,  Kazunori Hikone ,  Seiji Kobayashi

发明人： Masahide Miyazaki ,  Kazumi Hatayama ,  Kazunori Hikone ,  Seiji Kobayashi

IPC分类号： G06F1125

CPC分类号： G11C29/16

摘要： The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.

摘要翻译： 本发明涉及根据存储在片上存储器中的测试程序使用其内置测试功能进行自检的LSI。 本发明的目的是在分支到片上存储器的地址空间中的地址发生的情况下有效地执行自检。程序计数器101存储存储器117和外部存储器的地址。 测试程序计数器108存储存储器117的地址。在测试模式中，程序计数器切换部109执行控制，使得当在程序计数器101中检测到存储器117的地址时，程序计数器的地址值 101，而当在程序计数器101中检测到外部存储器的地址时，选择测试程序计数器108的地址值。 签名压缩电路110签名压缩并保持程序计数器101的输出值。

公开(公告)号：US06317853B1

公开(公告)日：2001-11-13

申请号：US08847592

申请日：1997-04-24

申请人： Kazunori Hikone ,  Kazumi Hatayama ,  Takao Nishida ,  Hiromichi Yamada

发明人： Kazunori Hikone ,  Kazumi Hatayama ,  Takao Nishida ,  Hiromichi Yamada

IPC分类号： G01R3128

CPC分类号： G06F11/263

摘要： An apparatus for providing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed. The apparatus also has an instruction sequence producing part for producing an instruction sequence in a machine language for the processor LSI by which an output from the block edge of the functional block becomes detectable at an external terminal of the processor LSI.

摘要翻译： 一种用于提供用于检测在处理器LSI的制造功能块中发生的缺陷的测试数据的装置，设置有用于根据逻辑数据检测在功能块的块边缘处的功能块的故障的测试模式产生部分 功能块的功能块的功能块的操作的一个操作对于要产生的测试数据的功能块的一个操作，功能块的块边缘处的测试图案要满足输入信号的条件 当执行一个操作的指令时，功能块的块边缘，以及当执行指令时来自处理器LSI的外部的可从功能块的块边缘输出的输出信号的条件。 该装置还具有指令序列生成部分，用于产生用于处理器LSI的机器语言的指令序列，通过该指令序列，功能块的块边沿的输出在处理器LSI的外部端可以检测到。