公开(公告)号：US20070234262A1

公开(公告)日：2007-10-04

申请号：US11523040

申请日：2006-09-19

申请人： Masato Uedi ,  Mamoru Sobue ,  Kouhei Nagaya ,  Takeshi Inoue ,  Yoshinori Gotou

发明人： Masato Uedi ,  Mamoru Sobue ,  Kouhei Nagaya ,  Takeshi Inoue ,  Yoshinori Gotou

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method for inspecting the layout of elements included in a semiconductor device. The method includes setting paired layout inspection requirements including at least an element interval at which a paired layout is enabled, inspecting whether or not the elements that are to be inspected for paired layout satisfy the paired layout inspection requirements, setting a search area for each of the elements that are to be inspected for paired layout, and extracting figures included in the search areas of the elements that are to be inspected for paired layout and inspecting whether or not the extracted figures of the elements that are to be inspected for paired layout are congruent to each other.

摘要翻译： 一种用于检查包括在半导体器件中的元件的布局的方法。 该方法包括设置配对布局检查要求，其包括至少一个启用配对布局的单元间隔，检查待检查的成对布局的元素是否满足配对布局检查要求，为每个布局检查要求设置搜索区域 要检查配对布局的元素，并且提取包括在要被检查的配对布局的元素的搜索区域中的图形，并且检查要被配对布局检查的元素的提取图形是否是 相互一致。