公开(公告)号：US5155855A

公开(公告)日：1992-10-13

申请号：US262908

申请日：1988-10-26

申请人： Yasuo Masuo ,  Masayuki Iwatsuka

发明人： Yasuo Masuo ,  Masayuki Iwatsuka

IPC分类号： G06F15/167

CPC分类号： G06F15/167

摘要： A multi-CPU system comprises between a CPU without a control terminal and a common memory: an access mediation latch for temporarily latching data information to be transferred and corresponding address information; and a timing control circuit for controlling the timing of data transfer between the access mediation latch and the common memory in accordance with a mediation signal outputted from a contention mediation terminal of the common memory.