公开(公告)号：US5155855A

公开(公告)日：1992-10-13

申请号：US262908

申请日：1988-10-26

申请人： Yasuo Masuo ,  Masayuki Iwatsuka

发明人： Yasuo Masuo ,  Masayuki Iwatsuka

IPC分类号： G06F15/167

CPC分类号： G06F15/167

摘要： A multi-CPU system comprises between a CPU without a control terminal and a common memory: an access mediation latch for temporarily latching data information to be transferred and corresponding address information; and a timing control circuit for controlling the timing of data transfer between the access mediation latch and the common memory in accordance with a mediation signal outputted from a contention mediation terminal of the common memory.

公开(公告)号：US5862405A

公开(公告)日：1999-01-19

申请号：US751329

申请日：1996-11-18

申请人： Atsuo Fukuda ,  Yasuo Masuo

发明人： Atsuo Fukuda ,  Yasuo Masuo

IPC分类号： G06F13/14 ,  G06F13/10 ,  G06F13/00

CPC分类号： G06F13/14

摘要： A unit address is automatically set in a peripheral unit. A plurality of peripheral units 1 are connected to a CPU unit via a signal line 3. The CPU unit accesses each peripheral unit 1 by individually selecting the peripheral units. The signal line 3 is provided with a first signal line 31 for transmitting an address by bus connection of the peripheral units and a second signal 32 line for transmitting a write command signal by cascade connection of the peripheral units 1. The write command signal is sequentially transmitted in the order in which the peripheral units 1 are connected, and only the peripheral unit 1 that has received the write command signal receives a unit address and retains it in a latch circuit 11a.

摘要翻译： 单元地址在外设中自动设置。 多个外围单元1经由信号线3连接到CPU单元。CPU单元通过单独选择外围单元来访问每个外围单元1。 信号线3设置有用于通过外围单元的总线连接发送地址的第一信号线31和用于通过外围单元1的级联连接来发送写入命令信号的第二信号32线。写入命令信号是顺序地 以外围单元1连接的顺序发送，只有接收到写入命令信号的外围单元1接收单元地址并将其保存在锁存电路11a中。