公开(公告)号：US09148135B2

公开(公告)日：2015-09-29

申请号：US13532881

申请日：2012-06-26

申请人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： G06F1/00 ,  H03K5/156 ,  G06F1/08

CPC分类号： H03K5/1565 ,  G06F1/08

摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

摘要翻译： 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

公开(公告)号：US08963649B2

公开(公告)日：2015-02-24

申请号：US13731687

申请日：2012-12-31

申请人： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03L1/00 ,  H03L7/06 ,  H03B5/10

CPC分类号： H03L1/00 ,  H03B5/10 ,  H03L7/06 ,  H03L7/099 ,  H03L7/0992

摘要： A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

摘要翻译： 压控振荡器（VCO）包括电流控制振荡器，电压 - 电流转换器和感测电路。 感测电路包括延迟单元，并且感测电路被配置为响应于延迟单元的时间延迟而产生多个补偿控制信号。 电压 - 电流转换器被配置为响应于VCO控制信号和多个补偿控制信号而产生电流信号。 电流控制振荡器被配置为响应于当前信号产生振荡信号。

公开(公告)号：US20130342252A1

公开(公告)日：2013-12-26

申请号：US13532881

申请日：2012-06-26

申请人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  G06F1/08

摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

摘要翻译： 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。