Structure for dynamic latch state saving device and protocol
    1.
    发明授权
    Structure for dynamic latch state saving device and protocol 有权
    动态锁存状态保存装置和协议的结构

    公开(公告)号:US07966589B2

    公开(公告)日:2011-06-21

    申请号:US12099423

    申请日:2008-04-08

    CPC classification number: G11C5/145 H03K3/356008

    Abstract: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

    Abstract translation: 本发明包括一种用于动态电压状态保存锁存电路的设计结构,其包括适于作为存储元件的充电装置,集成恢复机构,连接到充电装置的电源电压轨,分配给集成恢复机构的保持信号 ,分配给所述充电装置的数据信号输入,从充电装置分配的数据信号和分配给充电装置的时钟信号,其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

    DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL
    2.
    发明申请
    DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL 有权
    动态锁定状态节省设备和协议的设计结构

    公开(公告)号:US20080186069A1

    公开(公告)日:2008-08-07

    申请号:US12099423

    申请日:2008-04-08

    CPC classification number: G11C5/145 H03K3/356008

    Abstract: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

    Abstract translation: 本发明包括一种用于动态电压状态保存锁存电路的设计结构,其包括适于作为存储元件的充电装置,集成恢复机构,连接到充电装置的电源电压轨,分配给集成恢复机构的保持信号 ,分配给所述充电装置的数据信号输入,从充电装置分配的数据信号和分配给充电装置的时钟信号,其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

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