公开(公告)号：US20090251474A1

公开(公告)日：2009-10-08

申请号：US12099183

申请日：2008-04-08

Applicant: Deanna J. Chou ,  Jesse E. Craig ,  Pascal A. Nsame ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

Inventor： Deanna J. Chou ,  Jesse E. Craig ,  Pascal A. Nsame ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC: G06T1/00

CPC classification number: G06T15/005 ,  G06T2200/16

Abstract: A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of graphic commands. The system further includes at least one communication network which directly receives the graphics processing unit command stream from each of the microprocessor-based devices and transfers each of the generated graphics processing unit command streams via a respective active channel, at least one multi-core adaptive display server which receives and processes the graphics processing unit command streams, and at least one display which receives the packets via the at least one active channel per user session and displays at least one image. The at least one active channel connects a respective microprocessor-based device, the communication network, the at least one multi-core adaptive display server and the at least one display.

Abstract translation: 虚拟计算和显示系统及方法。 该系统包括运行软件应用的多个基于微处理器的设备，并且每个基于微处理器的设备生成包括图形命令的分组的至少一个图形处理单元命令流。 该系统还包括至少一个通信网络，其直接从每个基于微处理器的设备接收图形处理单元命令流，并经由相应的活动信道传送每个生成的图形处理单元命令流，至少一个多核自适应 显示服务器，其接收和处理图形处理单元命令流，以及至少一个显示器，其通过每个用户会话的至少一个活动频道接收分组并显示至少一个图像。 所述至少一个活动通道连接相应的基于微处理器的设备，通信网络，至少一个多核自适应显示服务器和至少一个显示器。

公开(公告)号：US20070271449A1

公开(公告)日：2007-11-22

申请号：US11419388

申请日：2006-05-19

Applicant: Susan K. Lichtensteiger ,  Pascal A. Nsame ,  Sebastian T. Ventrone

Inventor： Susan K. Lichtensteiger ,  Pascal A. Nsame ,  Sebastian T. Ventrone

IPC: G06F9/44

CPC classification number: G06F9/3869 ,  G06F9/3836 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3873

Abstract: A system for dynamically varying the pipeline depth of a computing device, depending upon at least one of computing function and workload, includes a state machine is configured to determine an optimum length of a pipeline architecture based on a processing function to be performed, and a pipeline sequence controller, responsive to the state machine, the pipeline sequence controller configured to vary the depth of the pipeline based on the determined optimum length. A plurality of clock splitter elements is associated with a corresponding plurality of latch stages in the pipeline architecture, the clock splitter elements coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

Abstract translation: 根据计算功能和工作负载中的至少一个动态地改变计算设备的流水线深度的系统包括状态机被配置为基于要执行的处理功能来确定流水线架构的最佳长度，以及 流水线序列控制器，响应于状态机，配置为基于所确定的最佳长度来改变管道的深度的流水线序列控制器。 多个时钟分离器元件与流水线架构中的对应的多个锁存级相关联，时钟分离器元件耦合到流水线序列控制器并且适于以功能模式操作，一个或多个时钟选通模式， 通过冲洗模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。

公开(公告)号：US09367493B2

公开(公告)日：2016-06-14

申请号：US11275091

申请日：2005-12-09

Applicant: Robert J. Devins ,  David W. Milton ,  Pascal A. Nsame

Inventor： Robert J. Devins ,  David W. Milton ,  Pascal A. Nsame

IPC: G06F15/173 ,  G06F13/24 ,  G06F15/17

CPC classification number: G06F13/24 ,  G06F15/17

Abstract: A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.

Abstract translation: 一种方法和系统包括将数据从第一处理器传送到直接连接到至少第二处理器的中断控制的至少一个脉冲发生器。 数据传输绕过内存。 该方法还包括由至少第二处理器直接从至少一个脉冲发生器读取传送的数据。

公开(公告)号：US08729920B2

公开(公告)日：2014-05-20

申请号：US12953828

申请日：2010-11-24

Applicant: Carole D. Graas ,  Keith A. Jenkins ,  Pascal A. Nsame ,  Kevin G. Stawiasz

Inventor： Carole D. Graas ,  Keith A. Jenkins ,  Pascal A. Nsame ,  Kevin G. Stawiasz

IPC: G01R31/26

CPC classification number: G11C29/50 ,  G01R31/2882 ,  G11C16/349 ,  G11C2029/5002

Abstract: Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product.

Abstract translation: 为可靠性，可用性和可服务性（RAS）使能和半自动调节频率和延迟传感器提供了电路和方法。 用于测量和补偿集成电路的时间依赖性能劣化的电路包括集成电路的至少一个关键功能路径和连接到关键功能路径边界的扰动隔离寄存器（WIR）。 电路还包括连接到WIR的反馈路径，以及传感器控制模块，其可操作以将关键功能路径与集成电路的先前和后续功能路径断开连接，将关键功能路径连接到反馈路径以形成关键路径环 振荡器（CPRO），并使CPRO产生操作信号。 延迟传感器模块可操作以测量操作信号的频率，以确定并补偿半导体产品的寿命期间的应用性能的劣化。

公开(公告)号：US20120126870A1

公开(公告)日：2012-05-24

申请号：US12953828

申请日：2010-11-24

Applicant: Carole D. GRAAS ,  Keith A. JENKINS ,  Pascal A. NSAME ,  Kevin G. STAWIASZ

Inventor： Carole D. GRAAS ,  Keith A. JENKINS ,  Pascal A. NSAME ,  Kevin G. STAWIASZ

IPC: H03H11/26

CPC classification number: G11C29/50 ,  G01R31/2882 ,  G11C16/349 ,  G11C2029/5002

Abstract: Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product.

Abstract translation: 为可靠性，可用性和可服务性（RAS）使能和半自动调节频率和延迟传感器提供了电路和方法。 用于测量和补偿集成电路的时间依赖性能劣化的电路包括集成电路的至少一个关键功能路径和连接到关键功能路径边界的扰动隔离寄存器（WIR）。 电路还包括连接到WIR的反馈路径，以及传感器控制模块，其可操作以将关键功能路径与集成电路的先前和后续功能路径断开连接，将关键功能路径连接到反馈路径以形成关键路径环 振荡器（CPRO），并使CPRO产生操作信号。 延迟传感器模块可操作以测量操作信号的频率，以确定并补偿半导体产品的寿命期间的应用性能的劣化。

公开(公告)号：US07711534B2

公开(公告)日：2010-05-04

申请号：US11275093

申请日：2005-12-09

Applicant: Robert J. Devins ,  David W. Milton ,  Pascal A. Nsame

Inventor： Robert J. Devins ,  David W. Milton ,  Pascal A. Nsame

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F11/3688

Abstract: A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.

Abstract translation: 一种方法和系统包括提取在设计上运行离散测试用例或相关测试用例的集合所需的资源。 该方法和系统还包括基于所提取的资源构建仿真模型，并且仅使用所提取的资源（不包括整个设计）来执行仿真模型，以测试由离散测试用例或集合表示的特定功能或相关联的功能组 的相关测试用例进行设计验证，并将仿真结果与测试计划相关联。

公开(公告)号：US20080186069A1

公开(公告)日：2008-08-07

申请号：US12099423

申请日：2008-04-08

Applicant: Pascal A. Nsame ,  Anthony J. Perri ,  Lansing D. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Welland

Inventor： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing D. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Welland

IPC: H03K3/00

CPC classification number: G11C5/145 ,  H03K3/356008

Abstract: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Abstract translation: 本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号 ，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

公开(公告)号：US20080062748A1

公开(公告)日：2008-03-13

申请号：US11530981

申请日：2006-09-12

Applicant: Pascal A. Nsame ,  Anthony J. Perri ,  Lansing U. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Walland

Inventor： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing U. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Walland

IPC: G11C11/00

CPC classification number: G11C5/141 ,  G11C5/143 ,  G11C14/00

Abstract: The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Abstract translation: 本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号 分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。

公开(公告)号：US09557378B2

公开(公告)日：2017-01-31

申请号：US13553986

申请日：2012-07-20

Applicant: Jeanne P. Bickford ,  Vikram Iyengar ,  Rahul K. Nadkarni ,  Pascal A. Nsame

Inventor： Jeanne P. Bickford ,  Vikram Iyengar ,  Rahul K. Nadkarni ,  Pascal A. Nsame

IPC: H01L21/66 ,  G01R31/02 ,  G06F19/00 ,  G01R31/317 ,  G06F1/32

CPC classification number: G01R31/31718 ,  G01R31/31725 ,  G06F1/32

Abstract: Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.

Abstract translation: 测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。 将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。 对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。 特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。 该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。 为器件建立芯片专用功能电压限制。 来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

公开(公告)号：US08499140B2

公开(公告)日：2013-07-30

申请号：US13325307

申请日：2011-12-14

Applicant: Susan K. Lichtensteiger ,  Pascal A. Nsame ,  Sebastian T. Ventrone

Inventor： Susan K. Lichtensteiger ,  Pascal A. Nsame ,  Sebastian T. Ventrone

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F13/24 ,  G06F9/46

CPC classification number: G06F9/3869 ,  G06F1/04 ,  G06F1/3237 ,  G06F1/3243 ,  G06F9/3859 ,  G06F9/3873

Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

Abstract translation: 体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。 该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。 响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。 多个时钟分离器元件，每个与流水线架构中相应的多个锁存级联相关联，连接到流水线序列控制器，并适于在功能模式，一个或多个时钟选通模式和直通冲洗 模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。