公开(公告)号：US5851922A

公开(公告)日：1998-12-22

申请号：US865548

申请日：1997-05-29

Applicant: Joze Bevk ,  Matthias Werner Fuertsch ,  George E. Georgiou ,  Steven James Hillenius

Inventor： Joze Bevk ,  Matthias Werner Fuertsch ,  George E. Georgiou ,  Steven James Hillenius

IPC: H01L23/52 ,  H01L21/225 ,  H01L21/3205 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/76

CPC classification number: H01L21/823835

Abstract: The invention is directed to a process for forming p.sup.+ and n.sup.+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected to a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is performed after the n-type dopant is implanted into the structure. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n.sup.+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.

Abstract translation: 本发明涉及在单个衬底上形成p +和n +栅极的方法。 在其上形成有n型和p型区的衬底上形成多晶硅或非晶硅层，并在其上形成二氧化硅层，并且对该结构进行低温退火。 然后在结构上形成一层金属硅化物，并将n型和p型掺杂剂注入所得结构中。 在将n型掺杂剂注入结构中之后进行氮注入。 氮注入减少了p型掺杂剂通过硅化物层并进入n +栅极的量。 然后在结构上形成电介质材料并进行图案化，然后对该结构进行额外的处理步骤，以在衬底的n区和p区上形成栅叠层。