公开(公告)号：US5394000A

公开(公告)日：1995-02-28

申请号：US137453

申请日：1993-10-07

申请人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

发明人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

IPC分类号： H01L21/334 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L29/66181 ,  H01L27/10829

摘要： A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension. The narrow portion of the trench is filled by the first conductive layer and after planarization provides an area of sufficiently large dimension for forming a contact to the first electrode. Contact to the second electrode is made in the first portion of the trench. Thus multiple electrodes for a trench capacitor are defined by a maskless process.

摘要翻译： 提供一种形成用于集成电路的沟槽电容器的电极的方法，其中屏蔽电平的数量减少。 该方法与CMOS和双极CMOS工艺兼容。 在通过常规光刻步骤和各向异性蚀刻在衬底中限定沟槽之后，沉积第一介电层，第一导电层和随后的保形电介质层和共形导电层的连续共形层以填充沟槽。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 每个导电层形成电极。 每个导电层的共面区域在沟槽内露出以形成与电极的接触。 有利地，沟槽具有较小部分和较小横向尺寸的窄部分。 沟槽的狭窄部分由第一导电层填充，并且在平坦化之后提供足够大的尺寸的区域以形成与第一电极的接触。 在沟槽的第一部分中形成与第二电极的接触。 因此，通过无掩模工艺来定义用于沟槽电容器的多个电极。

公开(公告)号：US5275974A

公开(公告)日：1994-01-04

申请号：US921667

申请日：1992-07-30

申请人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

发明人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

IPC分类号： H01L21/334 ,  H01L27/108 ,  H01L21/62

CPC分类号： H01L29/66181 ,  H01L27/10829

摘要： A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension. The narrow portion of the trench is filled by the first conductive layer and after planarization provides an area of sufficiently large dimension for forming a contact to the first electrode. Contact to the second electrode is made in the first portion of the trench. Thus multiple electrodes for a trench capacitor are defined by a maskless process.

摘要翻译： 提供一种形成用于集成电路的沟槽电容器的电极的方法，其中屏蔽电平的数量减少。 该方法与CMOS和双极CMOS工艺兼容。 在通过常规光刻步骤和各向异性蚀刻在衬底中限定沟槽之后，沉积第一介电层，第一导电层和随后的保形电介质层和共形导电层的连续共形层以填充沟槽。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 每个导电层形成电极。 每个导电层的共面区域在沟槽内露出以形成与电极的接触。 有利地，沟槽具有较小部分和较小横向尺寸的窄部分。 沟槽的狭窄部分由第一导电层填充，并且在平坦化之后提供足够大的尺寸的区域以形成与第一电极的接触。 在沟槽的第一部分中形成与第二电极的接触。 因此，通过无掩模工艺来定义用于沟槽电容器的多个电极。