公开(公告)号：US6114227A

公开(公告)日：2000-09-05

申请号：US280258

申请日：1999-03-29

Applicant: David Leksell ,  Ming Xi Chan ,  Joseph P. Ellul ,  Jeanne L. Luce ,  David T. Ryan ,  Iqbal A. Shareef ,  Chung J. Lee ,  Stephen M. Campbell ,  Giovanni Antonio Foggiato

Inventor： David Leksell ,  Ming Xi Chan ,  Joseph P. Ellul ,  Jeanne L. Luce ,  David T. Ryan ,  Iqbal A. Shareef ,  Chung J. Lee ,  Stephen M. Campbell ,  Giovanni Antonio Foggiato

IPC: C23C16/44 ,  C23C16/455 ,  H01L21/205 ,  H01L21/20

CPC classification number: C23C16/45502 ,  C23C16/4401 ,  C23C16/455 ,  C23C16/45563

Abstract: This invention relates to the design of apparatus for processing electronic devices, including equipment for chemical vapor deposition or transport polymerization. The new designs of gas separator plates, their configuration, and the regulation of gas flows through the system provides control over the pattern of precursor gas flow away from the separation plates, thereby decreasing the amount of byproducts that are deposited on the plates and throughout the reactor. New designs for shaping other surfaces of the dispersion head reduces contamination of those elements, and new designs for chamber panels decrease the deposition of byproducts on those surfaces, as well as other elements of the reactor. Decreasing deposition of byproducts increases the amount and the quality of the film that can be deposited without requiring the system to be shut down for cleaning. This increases the throughput of products in the deposition process, thereby increasing the efficiency of electronic device manufacture and lowering the cost.

Abstract translation: 本发明涉及用于处理电子设备的装置的设计，包括用于化学气相沉积或运输聚合的设备。 气体分离器板的新设计，其结构和通过系统的气体流量的调节提供了控制离开分离板的前体气体流动的模式，从而减少了沉积在板上和整个过程中的副产物的量 反应堆。 用于成型分散头的其它表面的新设计减少了这些元件的污染，并且用于室板的新设计降低了在那些表面上以及反应器的其它元件的副产物的沉积。 副产物的沉积减少增加了可以沉积的膜的量和质量，而不需要系统关闭清洁。 这增加了沉积工艺中产品的生产量，从而提高了电子设备制造的效率并降低了成本。

公开(公告)号：US5362669A

公开(公告)日：1994-11-08

申请号：US80544

申请日：1993-06-24

Applicant: John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

Inventor： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L21/31053 ,  H01L21/76229 ,  H01L21/763 ,  Y10S148/05

Abstract: A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

Abstract translation: 提供了一种用于在用于集成电路的半导体衬底中形成完全平坦化的沟槽隔离区域的方法，例如沟槽隔离场氧化物区域或其中形成薄膜半导体器件的沟槽隔离半导体区域。 通过化学机械抛光工艺实现平面化，其中化学机械耐光材料的共面层设置在宽沟槽的中心区域以及邻近沟槽的半导体衬底表面上。 在宽沟槽的中心区域中的化学机械耐光层形成蚀刻停止件，以防止在通过化学机械抛光的整个晶片平面化期间填充沟槽的层的凹陷。 该方法兼容CMOS，双极和双极CMOS工艺，用于亚微米VLSI和ULSI集成电路结构。

公开(公告)号：US4859303A

公开(公告)日：1989-08-22

申请号：US106213

申请日：1987-10-09

Applicant: Alexander Kalnitsky ,  Joseph P. Ellul ,  Sing P. Tay ,  Jacques G. Poirier

Inventor： Alexander Kalnitsky ,  Joseph P. Ellul ,  Sing P. Tay ,  Jacques G. Poirier

IPC: B44D3/16 ,  G03F7/42 ,  H01J37/32

CPC classification number: H01J37/32357 ,  B44D3/168 ,  G03F7/427 ,  H01J2237/004

Abstract: In a method and apparatus for plasma stripping a polymer photoresist coating from a semiconductor substrate, positively charged species are removed from an activated gas flow before the gas flow is brought into contact with the coating to strip the coating from the substrate. The positively charged species may be removed by bringing the activated gas into contact with a grounded conducting surface to discharge the positively charged species, or by passing the activated gas through a negatively charged electrostatic filter to filter out positively charged species. The removal of positively charged species from the gas flow reduces or eliminates build up of positive charge on an outer surface of the photoresist coating so as to avoid driving mobile positively charged ions from the photoresist into the substrate, thereby avoiding contamination of the substrate.

Abstract translation: 在用于从半导体衬底等离子体剥离聚合物光刻胶涂层的方法和装置中，在使气流与涂层接触以从衬底剥离涂层之前，从活性气体流中除去带正电的物质。 可以通过使活化气体与接地的导电表面接触以排出带正电的物质或通过使活化气体通过带负电的静电过滤器以过滤带正电的物质来除去带正电的物质。 从气流中去除带正电荷的物质减少或消除在光致抗蚀剂涂层的外表面上的正电荷的积累，以避免驱动移动的带正电荷的离子从光致抗蚀剂进入衬底，从而避免衬底的污染。

公开(公告)号：US4836902A

公开(公告)日：1989-06-06

申请号：US106214

申请日：1987-10-09

Applicant: Alexander Kalnitsky ,  Joseph P. Ellul ,  Sing P. Tay

Inventor： Alexander Kalnitsky ,  Joseph P. Ellul ,  Sing P. Tay

IPC: G03F7/42 ,  H01J37/32 ,  H01L21/311

CPC classification number: H01J37/32871 ,  G03F7/427 ,  H01L21/31138

Abstract: In a method and apparatus for plasma stripping a polymer photoresist coating from a semiconductor substrate, ultraviolet radiation generated as a byproduct of plasma generation is absorbed by a baffle placed between a plasma source and the substrate. The baffle inhibits incidence of ultraviolet light on the substrate while permitting flow of activated gas onto the substrate to chemically strip the photoresist from the substrate. Use of the baffle reduces microscopic damage to the substrate.

Abstract translation: 在用于从半导体衬底等离子体剥离聚合物光刻胶涂层的方法和装置中，作为等离子体产生的副产物产生的紫外线辐射被置于等离子体源和衬底之间的挡板吸收。 挡板抑制基板上的紫外光的入射，同时允许活性气体流到基板上以从基板上化学剥离光致抗蚀剂。 挡板的使用减少了对基材的微观损伤。

公开(公告)号：US6079353A

公开(公告)日：2000-06-27

申请号：US50228

申请日：1998-03-28

Applicant: David Leksell ,  Ming Xi Chan ,  Joseph P. Ellul ,  Jeanne L. Luce ,  David T. Ryan ,  Iqbal A. Shareef ,  Chung J. Lee ,  Giovanni Antonio Foggiato

Inventor： David Leksell ,  Ming Xi Chan ,  Joseph P. Ellul ,  Jeanne L. Luce ,  David T. Ryan ,  Iqbal A. Shareef ,  Chung J. Lee ,  Giovanni Antonio Foggiato

IPC: C23C16/44 ,  C23C16/455 ,  H01L21/205 ,  C23C16/00

CPC classification number: C23C16/45502 ,  C23C16/4401 ,  C23C16/455 ,  C23C16/45563

Abstract: This invention relates to the design of apparatus for processing electronic devices, including equipment for chemical vapor deposition. The new designs of gas separator plates, their configuration, and the regulation of gas flows through the system provides control over the pattern of precursor gas flow away from the separation plates, thereby decreasing the amount of byproducts that are deposited on the plates and throughout the reactor. New designs for shaping other surfaces of the dispersion head reduces contamination of those elements, and new designs for chamber panels decrease the deposition of byproducts on those surfaces, as well as other elements of the reactor. Decreasing deposition of byproducts increases the amount of thin film, and the quality of the film which can be deposited without requiring the system to be shut down. This increases the throughput of products in the deposition process, thereby increasing the efficiency of electronic device manufacture and lowering the cost.

Abstract translation: 本发明涉及用于处理电子设备的装置的设计，包括用于化学气相沉积的设备。 气体分离器板的新设计，其结构和通过系统的气体流量的调节提供了控制离开分离板的前体气体流动的模式，从而减少了沉积在板上和整个过程中的副产物的量 反应堆。 用于成型分散头的其它表面的新设计减少了这些元件的污染，并且用于室板的新设计降低了在那些表面上以及反应器的其它元件的副产物的沉积。 副产物的沉积减少增加了薄膜的量，以及可以在不需要系统关闭的情况下沉积的膜的质量。 这增加了沉积工艺中产品的生产量，从而提高了电子设备制造的效率并降低了成本。

公开(公告)号：US5773871A

公开(公告)日：1998-06-30

申请号：US638084

申请日：1996-04-25

Applicant: John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

Inventor： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC: H01L21/3105 ,  H01L21/763 ,  H01L29/00

CPC classification number: H01L21/763 ,  H01L21/31053

Abstract: An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract translation: 提供一种集成电路结构及其制造方法。 特别地，完全平坦化的沟槽隔离半导体区域，例如， 包括掺杂多晶硅，设置在集成电路基板中。 这些多晶硅区域具有通过化学机械抛光提供的平滑表面，与基板表面基本上共面。 近零地形衬底提供在其上形成集成电路结构，包括例如。 电容器，电阻器，薄膜电容器和互连，在与半导体衬底中形成的器件相同的工艺级别的多晶硅沟槽区域中。 因此，提供了用于形成改进的器件结构的简单且灵活的工艺，与已知的双极，CMOS和双极CMOS工艺兼容。

公开(公告)号：US5516710A

公开(公告)日：1996-05-14

申请号：US339184

申请日：1994-11-10

Applicant: John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

Inventor： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC: H01L21/331 ,  H01L21/60 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L21/28114 ,  H01L21/76897 ,  H01L29/0804 ,  H01L29/42376 ,  H01L29/66272

Abstract: A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure. The resulting structure is fully planarized, preferably by chemical mechanical polishing, to form coplanar contact areas to the base and emitter.

Abstract translation: 提供了一种用于形成用于双极，CMOS或双极CMOS集成电路的晶体管的方法。 该方法适用于使用单个掩模步骤形成双重多晶硅自对准双极晶体管，用于限定具有窄的发射极 - 基极接触面积和大的发射极接触面积的发射极结构。 该方法包括选择性地提供电介质的锥形体以掩盖其上将形成发射极的衬底的区域。 导电层设置在锥体周围以形成基底接触电极。 锥形体从衬底选择性地移除，而不会损坏下面的硅衬底，留下锥形开口; 在第一导电层上以侧壁间隔物的形式提供局部介电隔离。 锥形开口填充有第二导电材料层以形成第二电极，即发射极结构。 所得到的结构完全平坦化，优选通过化学机械抛光，以形成与基底和发射体的共面接触面。

公开(公告)号：US5352923A

公开(公告)日：1994-10-04

申请号：US105240

申请日：1993-08-12

Applicant: John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

Inventor： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC: H01L21/02 ,  H01L27/02

CPC classification number: H01L28/20 ,  Y10S148/136

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

Abstract translation: 提供一种用于使用单个掩模级形成用于集成电路的多值线性电阻器的方法。 多个沟槽被限定在衬底中。 每个沟槽具有特定侧向尺寸的接触区域和在它们之间延伸的较窄部分。 提供第一电介质层，高电阻率的第一导电层和较低电阻率的第二导电层的连续共形层以填充沟槽。 填充沟槽的第二导电层的量取决于沟槽的宽度。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 有利地，当第一和第二导电层分别由未掺杂和掺杂的多晶硅层提供时，沟槽尺寸控制掺杂在沟槽的每个区域中的掺杂剂的量。 在退火到扩散掺杂剂之后，较宽的端部接触区域被重掺杂以形成接触区域，并且沟槽的中间窄部分被掺杂到取决于沟槽宽度的水平，由此形成具有电阻率相反的电阻元件 在沟槽宽度上。 该方法兼容CMOS，双极和双极CMOS工艺。

公开(公告)号：US5316978A

公开(公告)日：1994-05-31

申请号：US37048

申请日：1993-03-25

Applicant: John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

Inventor： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC: H01L21/02 ,  H01L21/3205 ,  H01L21/283

CPC classification number: H01L28/20 ,  Y10S148/136

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

Abstract translation: 提供一种用于使用单个掩模级形成用于集成电路的多值线性电阻器的方法。 多个沟槽被限定在衬底中。 每个沟槽具有特定侧向尺寸的接触区域和在它们之间延伸的较窄部分。 提供第一电介质层，高电阻率的第一导电层和较低电阻率的第二导电层的连续共形层以填充沟槽。 填充沟槽的第二导电层的量取决于沟槽的宽度。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 有利地，当第一和第二导电层分别由未掺杂和掺杂的多晶硅层提供时，沟槽尺寸控制掺杂在沟槽的每个区域中的掺杂剂的量。 在退火到扩散掺杂剂之后，较宽的端部接触区域被重掺杂以形成接触区域，并且沟槽的中间窄部分被掺杂到取决于沟槽宽度的水平，由此形成具有电阻率相反的电阻元件 在沟槽宽度上。 该方法兼容CMOS，双极和双极CMOS工艺。

公开(公告)号：US08847365B2

公开(公告)日：2014-09-30

申请号：US13677061

申请日：2012-11-14

Applicant: Joseph P. Ellul ,  Khanh Tran ,  Edward Martin Godshalk ,  Albert Bergemont

Inventor： Joseph P. Ellul ,  Khanh Tran ,  Edward Martin Godshalk ,  Albert Bergemont

IPC: H01L29/86 ,  H01L21/786 ,  H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract translation: 用于集成电路的电感器和方法，其导致尺寸与集成电路兼容的电感器，允许制造电感器，在第一晶片上具有或不具有附加电路，以及将晶片连接到第二晶片，而不浪费晶片面积。 第一晶片中的电感器由在第一晶片的每个表面处的导体形成的线圈组成，该线圈与穿过第一晶片的孔中的导体相连接。 公开了各种实施例。