公开(公告)号：US20060014330A1

公开(公告)日：2006-01-19

申请号：US10537092

申请日：2003-12-01

申请人： Masashi Ichikawa ,  Takeshi Kobayashi ,  Miho Iwabuchi

发明人： Masashi Ichikawa ,  Takeshi Kobayashi ,  Miho Iwabuchi

IPC分类号： H01L21/84

CPC分类号： H01L21/76254 ,  H01L21/02043

摘要： The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers each with no line defect on a surface thereof are used. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers are subjected to a high temperature heat treatment in advance.

摘要翻译： 本发明提供一种SOI晶片的制造方法，该SOI晶片在制造SOI晶片时能够抑制空穴的产生。 在本发明的SOI晶片的制造方法中，准备两个起始晶片，在两个起始晶片中的至少一个上形成绝缘层，并且一个晶片不使用粘合剂粘附到另一个晶片上， 使用其表面上没有线缺陷的起始晶片。 在本发明的SOI晶片的制造方法中，准备两个起始晶片，在两个起始晶片中的至少一个上形成绝缘层，并且一个晶片不使用粘合剂粘附到另一个晶片上， 预先对起始晶片进行高温热处理。

公开(公告)号：US06861268B2

公开(公告)日：2005-03-01

申请号：US10111500

申请日：2001-08-21

申请人： Miho Iwabuchi

发明人： Miho Iwabuchi

IPC分类号： G01N21/956 ,  C09C1/30 ,  C30B29/06 ,  G01N21/95 ,  H01L21/02 ,  H01L21/304 ,  H01L21/66

CPC分类号： G01N21/9501 ,  C01P2006/12 ,  H01L22/12

摘要： The present invention provides a method for inspecting a silicon wafer making it possible to identify and efficiently detect a new defect affecting a device fabricating process, a method for manufacturing a silicon wafer enabling manufacture of wafers not having the defect, a method for fabricating a semiconductor device using the silicon wafer not having this defect, and the silicon wafer not having the defect. When a silicon wafer is inspected, inspection is made for a defect having the entire defect size of 0.5 μm or more in which microdefects gather in a colony state.

摘要翻译： 本发明提供了一种用于检查硅晶片的方法，其使得能够识别和有效地检测影响器件制造工艺的新缺陷，制造可以制造不具有缺陷的晶片的硅晶片的制造方法，半导体制造方法 使用不具有该缺陷的硅晶片的器件，以及不具有缺陷的硅晶片。 当检查硅晶片时，检查整个缺陷尺寸为0.5μm或更大的缺陷，其中微缺陷在集落状态下聚集。

公开(公告)号：US20070158653A1

公开(公告)日：2007-07-12

申请号：US10586953

申请日：2005-01-24

申请人： Makoto Iida ,  Toshihiko Imai ,  Katsuichi Sato ,  Miho Iwabuchi ,  Masahiro Kato

发明人： Makoto Iida ,  Toshihiko Imai ,  Katsuichi Sato ,  Miho Iwabuchi ,  Masahiro Kato

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： C30B29/06 ,  C30B15/00 ,  C30B15/10

摘要： The present invention is a silicon single crystal grown by CZ method, wherein Cu precipitates do not exist inside the silicon single crystal, a silicon wafer produced from the silicon single crystal, wherein Cu precipitates do not exist on a surface of and inside the wafer, and an apparatus for producing a silicon single crystal according to CZ method, wherein Cu concentration in a component made of quartz to be used in a part in which a temperature in a furnace for single crystal growth is 1000° C. or more is 1 ppb or less, and Cu concentration in a component made of quartz to be used in a part in which a temperature in a furnace for single crystal growth is less than 1000° C. is 10 ppb or less, and a method for producing a silicon single crystal by using the producing apparatus. Thereby, there are provided a silicon single crystal and a silicon wafer which have extremely few crystal defects and have high quality and high yield, a producing apparatus therefor, and a producing method therefor.

摘要翻译： 本发明是通过CZ法生长的硅单晶，其中在硅单晶内部不存在Cu析出物，由硅单晶制造的硅晶片，其中在晶片的表面和晶片内部不存在Cu析出物， 以及根据CZ法制造硅单晶的装置，其中在用于单晶生长炉的温度为1000℃以上的部分中使用的石英成分中的Cu浓度为1ppb 在单晶生长用炉内的温度小于1000℃的部分中使用的石英成分中的Cu浓度为10ppb以下，制造硅单体的方法 晶体。 由此，提供了具有极少的晶体缺陷并具有高质量和高产率的硅单晶和硅晶片及其制造装置及其制造方法。

公开(公告)号：US07276427B2

公开(公告)日：2007-10-02

申请号：US10537092

申请日：2003-12-01

申请人： Masashi Ichikawa ,  Takeshi Kobayashi ,  Miho Iwabuchi

发明人： Masashi Ichikawa ,  Takeshi Kobayashi ,  Miho Iwabuchi

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  H01L21/02043

摘要： The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers each with no line defect on a surface thereof are used. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers are subjected to a high temperature heat treatment in advance.

摘要翻译： 本发明提供一种SOI晶片的制造方法，该SOI晶片在制造SOI晶片时能够抑制空穴的产生。 在本发明的SOI晶片的制造方法中，准备两个起始晶片，在两个起始晶片中的至少一个上形成绝缘层，并且一个晶片不使用粘合剂粘附到另一个晶片上， 使用其表面上没有线缺陷的起始晶片。 在本发明的SOI晶片的制造方法中，准备两个起始晶片，在两个起始晶片中的至少一个上形成绝缘层，并且一个晶片不使用粘合剂粘附到另一个晶片上， 预先对起始晶片进行高温热处理。

公开(公告)号：US20060154445A1

公开(公告)日：2006-07-13

申请号：US10525397

申请日：2003-08-21

申请人： Miho Iwabuchi

发明人： Miho Iwabuchi

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  H01L27/1203

摘要： The present invention provides a method for manufacturing an SOI wafer with high productivity in which generation of voids is suppressed in manufacturing the SOI wafer. The present invention comprises the steps of: forming an insulating layer on at least one wafer of two starting wafers; and adhering the one wafer to the other wafer without using an adhesive, wherein a PV value of a surface of the insulating layer is 1.5 nm or less.

摘要翻译： 本发明提供一种制造SOI晶片的SOI晶片的制造方法，该SOI晶片在制造SOI晶片时抑制空穴的产生。 本发明包括以下步骤：在两个起始晶片的至少一个晶片上形成绝缘层; 并且在不使用粘合剂的情况下将一个晶片粘附到另一个晶片，其中绝缘层的表面的PV值为1.5nm以下。