公开(公告)号：US6040223A

公开(公告)日：2000-03-21

申请号：US373636

申请日：1999-08-13

申请人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

发明人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO.sub.2 stress-release layer is deposited having a trapezoidal shape. A Si.sub.3 N.sub.4 layer is deposited and plasma etched back using the SiO.sub.2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO.sub.2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si.sub.3 N.sub.4 also extends over the SiO.sub.2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO.sub.2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si.sub.3 N.sub.4 extending over the portion of the trapezoidal-shaped SiO.sub.2 layer that forms part of the composite sidewall spacer protects the SiO.sub.2 from etching. This results in more reliable contacts without degrading the FET performance.

摘要翻译： 实现了具有复合侧壁间隔物的改进的多晶硅FET栅电极的方法。 在基板上形成多晶硅栅电极之后，沉积具有梯形形状的SiO 2应力释放层。 沉积Si 3 N 4层并使用SiO 2层等离子体蚀刻回蚀刻端点检测层，以形成包括梯形氧化物层的部分的复合侧壁间隔物。 SiO 2层保护源极/漏极区域免受可能导致高漏电流的等离子体蚀刻损伤。 Si 3 N 4也在多晶硅栅电极的上边缘处在SiO 2层上延伸。 当使用氢氟酸湿蚀刻从剩余的氧化物从源极/漏极区域移除时，这防止了沿着栅电极的SiO 2的侵蚀。 当绝缘层沉积在FET上方，并且自对准接触开口被蚀刻到源极/漏极区域并且在栅电极上延伸时，Si3N4延伸超过形成复合材料的一部分的梯形SiO 2层的部分 侧壁间隔件保护SiO 2免受蚀刻。 这导致更可靠的触点，而不会降低FET性能。