公开(公告)号：US08471617B2

公开(公告)日：2013-06-25

申请号：US12818127

申请日：2010-06-17

申请人： Minseok Choi

发明人： Minseok Choi

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.

摘要翻译： 为时钟和其他周期信号提供占空比纠错的电路，方法和装置。 一个例子提供了一种占空比校正，其可用于改善由延迟锁定环接收或由延迟锁定环产生的时钟信号的占空比。 该示例接收输入时钟信号并使用可变延迟元件来构造改进的占空比输出时钟信号。 检查输出时钟的占空比以确定延迟元件是否提供过多或不足的延迟。 然后调整延迟元件的延迟。 为了改善响应时间，逐次逼近技术用于确定调整通过延迟元件的延迟的计数的最高有效位。 为了提高精度，使用线性技术来调整计数的最低有效位。

公开(公告)号：US20120092336A1

公开(公告)日：2012-04-19

申请号：US13271458

申请日：2011-10-12

申请人： Choonsub KIM ,  Kisoo Ha ,  Jinyoung Oh ,  Minseok Choi

发明人： Choonsub KIM ,  Kisoo Ha ,  Jinyoung Oh ,  Minseok Choi

IPC分类号： G06T15/00

CPC分类号： G09G3/2946 ,  G09G3/003 ,  H04N13/341

摘要： A 3D plasma display includes a plasma display panel and a driver which implements an image on a screen of the plasma display panel in a frame including a plurality of subfields and transmits an emitter signal to 3D glasses. A time difference between the emitter signal and a start time point of the frame when an average power level (APL) is a first level is different from a time difference between the emitter signal and a start time point of the frame when the APL is a second level different from the first level.

摘要翻译： 3D等离子体显示器包括等离子体显示面板和驱动器，其在包括多个子场的帧中实现等离子体显示面板的屏幕上的图像，并将发射器信号发送到3D眼镜。 当平均功率电平（APL）为第一电平时，发射极信号与帧的起始时间点之间的时间差与APL为发射极信号和帧的开始时间点之间的时间差不同 第二级与第一级不同。

公开(公告)号：US20110309869A1

公开(公告)日：2011-12-22

申请号：US12818127

申请日：2010-06-17

申请人： Minseok Choi

发明人： Minseok Choi

IPC分类号： H03K5/04

CPC分类号： H03K5/1565

摘要： Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.

摘要翻译： 为时钟和其他周期信号提供占空比纠错的电路，方法和装置。 一个例子提供了一种占空比校正，其可用于改善由延迟锁定环接收或由延迟锁定环产生的时钟信号的占空比。 该示例接收输入时钟信号并使用可变延迟元件来构造改进的占空比输出时钟信号。 检查输出时钟的占空比以确定延迟元件是否提供过多或不足的延迟。 然后调整延迟元件的延迟。 为了改善响应时间，逐次逼近技术用于确定调整通过延迟元件的延迟的计数的最高有效位。 为了提高精度，使用线性技术来调整计数的最低有效位。