公开(公告)号：US20140002156A1

公开(公告)日：2014-01-02

申请号：US13534274

申请日：2012-06-27

申请人： Sandeep Dwivedi ,  Muniswara Reddy Vorugu ,  Nidhir Kumar

发明人： Sandeep Dwivedi ,  Muniswara Reddy Vorugu ,  Nidhir Kumar

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： An integrated circuit 2 operates using a digital signal having a duty cycle. Duty cycle correction circuitry 26, 28, 30 operate under control of digital correction values which adjust the duty cycle of the digital signal to a target duty cycle. Periodically, detection of the duty cycle output from the duty cycle correction circuitry 26, 28, 30 is performed to determine whether or not this has drifted outside of a threshold range of duty cycles and if necessary the digital correction value is changed to bring the duty cycle back within the threshold range. The duty cycle correction circuitry 26, 28, 30 employs common mode logic stages 44, 46 and an auxiliary current path 48 which is controlled in its impedance by the digital correction value. The auxiliary current path 48 applies an offset voltage within the common mode logic stage 44 which adjusts the duty cycle of the digital signal represented by the differential signals propagating through the common mode logic stage 44.

摘要翻译： 集成电路2使用具有占空比的数字信号进行操作。 占空比校正电路26,28,30在数字校正值的控制下操作，数字校正值将数字信号的占空比调整到目标占空比。 周期地，执行从占空比校正电路26,28,30输出的占空比的检测，以确定其是否漂移在占空比的阈值范围之外，如果需要，数字校正值被改变以使占空比 循环回到阈值范围内。 占空比校正电路26,28,30采用共模逻辑级44,46和辅助电流通路48，其通过数字校正值控制其阻抗。 辅助电流路径48在共模逻辑级44中施加偏移电压，该偏移电压调节由通过共模逻辑级44传播的差分信号表示的数字信号的占空比。