公开(公告)号：US09404966B2

公开(公告)日：2016-08-02

申请号：US13548238

申请日：2012-07-13

申请人： Sandeep Dwivedi ,  Betina Hold

发明人： Sandeep Dwivedi ,  Betina Hold

IPC分类号： G01R31/02 ,  G01R31/317 ,  G11C29/02 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C29/04

CPC分类号： G01R31/31718 ,  G01R31/31725 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

摘要： A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.

摘要翻译： 性能特征监测电路包括提供第一延迟路径的第一延迟电路，其中在该第一延迟路径上的数据值的传输导致根据性能特性而变化的第一延迟。 还包括参考延迟电路以提供参考延迟路径，其中数据值在参考延迟路径上的传输引起参考延迟。 参考延迟电路包括被配置为在参考延迟路径上提供电容负载的组件，以便产生对参考延迟的自补偿作用，该参考延迟使得参考延迟比对性能特性变化的第一延迟更不敏感。 然后根据第一延迟和参考延迟的比较，比较电路用于产生监控电路的输出信号。

公开(公告)号：US20100231268A1

公开(公告)日：2010-09-16

申请号：US12453889

申请日：2009-05-26

申请人： Nidhir Kumar ,  Sandeep Dwivedi ,  Tippana Hari Babu

发明人： Nidhir Kumar ,  Sandeep Dwivedi ,  Tippana Hari Babu

IPC分类号： H03K3/00

CPC分类号： H03K19/018528 ,  H04L25/0272

摘要： A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, whilst second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.

摘要翻译： 提供了一种低电压差分信号驱动器，其中第一输出节点和第二输出节点提供差分信号。 第一差速器转向开关电路根据差分输入信号进行切换，以通过电流源选择性地将第一输出节点连接到电压源，而第二差分转向电路根据差分输入信号的反向版本进行切换以连接 第二个输出节点通过电流源供电。 提供了摆动控制电路，其被配置为在差分输入信号的极性转换期间为电流源建立电流放电路径，从而保持第一输出节点和第二输出节点处的输出信号的对称转换速率。

公开(公告)号：US20140002156A1

公开(公告)日：2014-01-02

申请号：US13534274

申请日：2012-06-27

申请人： Sandeep Dwivedi ,  Muniswara Reddy Vorugu ,  Nidhir Kumar

发明人： Sandeep Dwivedi ,  Muniswara Reddy Vorugu ,  Nidhir Kumar

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： An integrated circuit 2 operates using a digital signal having a duty cycle. Duty cycle correction circuitry 26, 28, 30 operate under control of digital correction values which adjust the duty cycle of the digital signal to a target duty cycle. Periodically, detection of the duty cycle output from the duty cycle correction circuitry 26, 28, 30 is performed to determine whether or not this has drifted outside of a threshold range of duty cycles and if necessary the digital correction value is changed to bring the duty cycle back within the threshold range. The duty cycle correction circuitry 26, 28, 30 employs common mode logic stages 44, 46 and an auxiliary current path 48 which is controlled in its impedance by the digital correction value. The auxiliary current path 48 applies an offset voltage within the common mode logic stage 44 which adjusts the duty cycle of the digital signal represented by the differential signals propagating through the common mode logic stage 44.

摘要翻译： 集成电路2使用具有占空比的数字信号进行操作。 占空比校正电路26,28,30在数字校正值的控制下操作，数字校正值将数字信号的占空比调整到目标占空比。 周期地，执行从占空比校正电路26,28,30输出的占空比的检测，以确定其是否漂移在占空比的阈值范围之外，如果需要，数字校正值被改变以使占空比 循环回到阈值范围内。 占空比校正电路26,28,30采用共模逻辑级44,46和辅助电流通路48，其通过数字校正值控制其阻抗。 辅助电流路径48在共模逻辑级44中施加偏移电压，该偏移电压调节由通过共模逻辑级44传播的差分信号表示的数字信号的占空比。

公开(公告)号：US08502568B2

公开(公告)日：2013-08-06

申请号：US12805734

申请日：2010-08-17

申请人： Sandeep Dwivedi ,  Nidhir Kumar ,  Sridhar Cheruku

发明人： Sandeep Dwivedi ,  Nidhir Kumar ,  Sridhar Cheruku

IPC分类号： H03B1/00

CPC分类号： H03K19/00315 ,  H03K19/018571

摘要： An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

摘要翻译： 集成电路2包括用于接收输入信号PAD并将其转换为输出信号OUT的接收器电路4。 传导路径电路14将输入10耦合到第一节点16.缓冲器电路18耦合在第一节点16和承载输出信号Out的输出端12之间。 导电路径电路包括连接在输入端10和第一节点16之间的第一PMOS晶体管24和第二PMOS晶体管26.第一NMOS晶体管28连接在输入端10和第一节点16之间。第二PMOS晶体管 晶体管26耦合到输出端12以直接接收输出信号，从而当输入电压上升超过切换缓冲电路18的一定水平时，实现对节点16的充电的快速切断。

公开(公告)号：US20140015562A1

公开(公告)日：2014-01-16

申请号：US13548238

申请日：2012-07-13

申请人： Sandeep Dwivedi ,  Betina Hold

发明人： Sandeep Dwivedi ,  Betina Hold

IPC分类号： G01R31/26 ,  G01R31/00

CPC分类号： G01R31/31718 ,  G01R31/31725 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

摘要： A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.

摘要翻译： 性能特征监测电路包括提供第一延迟路径的第一延迟电路，其中在该第一延迟路径上的数据值的传输导致根据性能特性而变化的第一延迟。 还包括参考延迟电路以提供参考延迟路径，其中数据值在参考延迟路径上的传输引起参考延迟。 参考延迟电路包括被配置为在参考延迟路径上提供电容负载的组件，以便产生对参考延迟的自补偿作用，该参考延迟使得参考延迟比对性能特性变化的第一延迟更不敏感。 然后根据第一延迟和参考延迟的比较，比较电路用于产生监控电路的输出信号。

公开(公告)号：US20120044608A1

公开(公告)日：2012-02-23

申请号：US12805734

申请日：2010-08-17

申请人： Sandeep Dwivedi ,  Nidhir Kumar ,  Sridhar Cheruku

发明人： Sandeep Dwivedi ,  Nidhir Kumar ,  Sridhar Cheruku

IPC分类号： H02H3/20 ,  H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/018571

摘要： An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

摘要翻译： 集成电路2包括用于接收输入信号PAD并将其转换为输出信号OUT的接收器电路4。 传导路径电路14将输入10耦合到第一节点16.缓冲器电路18耦合在第一节点16和承载输出信号Out的输出端12之间。 导电路径电路包括连接在输入端10和第一节点16之间的第一PMOS晶体管24和第二PMOS晶体管26.第一NMOS晶体管28连接在输入端10和第一节点16之间。第二PMOS晶体管 晶体管26耦合到输出端12以直接接收输出信号，从而当输入电压上升超过切换缓冲电路18的一定水平时，实现对节点16的充电的快速切断。

公开(公告)号：US07924056B2

公开(公告)日：2011-04-12

申请号：US12453889

申请日：2009-05-26

申请人： Nidhir Kumar ,  Sandeep Dwivedi ,  Tippana Hari Babu

发明人： Nidhir Kumar ,  Sandeep Dwivedi ,  Tippana Hari Babu

IPC分类号： H03K19/08

CPC分类号： H03K19/018528 ,  H04L25/0272

摘要： A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, while second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.

摘要翻译： 提供了一种低电压差分信号驱动器，其中第一输出节点和第二输出节点提供差分信号。 第一差速器转向开关电路根据差分输入信号进行切换，以通过电流源选择性地将第一输出节点连接到电压源，而第二差分转向电路根据差分输入信号的反向版本进行切换以连接 第二个输出节点通过电流源供电。 提供了摆动控制电路，其被配置为在差分输入信号的极性转换期间为电流源建立电流放电路径，从而保持第一输出节点和第二输出节点处的输出信号的对称转换速率。