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公开(公告)号：US06334171B1
公开(公告)日：2001-12-25
申请号：US09292323
申请日：1999-04-15
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3851 , G06F12/0888
摘要： A system for write-combining uncacheable stores includes a memory order buffer, which receives first and second stores, and a data cache address and control, which receives the first and second stores from the memory order buffer. One of the memory order buffer and the data cache address and control determines whether the first and second stores are uncacheable and whether the first and second stores are contiguous in memory. If those conditions are satisfied, the data cache address and control write-combines the first and second stores before committing them to memory. The system may also apply additional conditions to determine whether the stores should be write-combined, for example requiring a minimum size for each store.
摘要翻译： 用于写入组合不可缓存存储的系统包括接收第一和第二存储的存储器顺序缓冲器以及从存储器顺序缓冲器接收第一和第二存储的数据高速缓存地址和控制。 存储器顺序缓冲器和数据高速缓存地址和控制之一确定第一和第二存储器是否不可缓存，以及存储器中第一和第二存储器是否连续。 如果满足这些条件，数据缓存地址和控制写入 - 将第一个和第二个存储合并到存储器之前。 系统还可以应用附加条件来确定商店是否应该被写入组合，例如对于每个商店需要最小尺寸。
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2.发明授权Maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses 有权通过检查未接收的加载指令的负载地址来监视存储地址来维护处理器的顺序公开(公告)号：US06687809B2
公开(公告)日：2004-02-03
申请号：US10279601
申请日：2002-10-24
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3834
摘要： An apparatus in a first processor includes a first data structure to store addresses of store instruction dispatched during a last predetermined number of cycles. The apparatus further includes logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure. The apparatus still further includes logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.
摘要翻译： 第一处理器中的装置包括第一数据结构，用于存储在最后预定次数周期期间调度的存储指令的地址。 该装置还包括用于确定正在执行的加载指令的加载地址是否与第一数据结构中的存储地址之一匹配的逻辑。 如果各个加载指令的加载地址与第一数据结构中的存储地址匹配，则该装置还包括重放相应加载指令的逻辑。
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3.发明授权Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses 失效通过检查未接收的负载指令的负载地址对窥探存储地址来维护处理器排序的方法，装置和系统公开(公告)号：US06484254B1
公开(公告)日：2002-11-19
申请号：US09475922
申请日：1999-12-30
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3834
摘要： According to one aspect of the invention, a method is provided in which store addresses of store instructions dispatched during a last predetermined number of cycles are maintained in a first data structure of a first processor. It is determined whether a load address of a first load instruction matches one of the store addresses in the first data structure. The first load instruction is replayed if the load address of the first load instruction matches one of the store addresses in the first data structure.
摘要翻译： 根据本发明的一个方面，提供了一种方法，其中在最后一个预定次数的周期期间调度的存储指令的存储地址保持在第一处理器的第一数据结构中。 确定第一加载指令的加载地址是否匹配第一数据结构中的一个存储地址。 如果第一个加载指令的加载地址与第一个数据结构中的一个存储地址匹配，则重播第一个加载指令。
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