公开(公告)号：US20080204080A1

公开(公告)日：2008-08-28

申请号：US12004739

申请日：2007-12-21

Applicant: Myoung-hoon Yoon ,  Sang-hoon Lee

Inventor： Myoung-hoon Yoon ,  Sang-hoon Lee

IPC: H03K19/10 ,  H03K19/0175

CPC classification number: H03K19/00315

Abstract: An inverting flip-flop (F/F) circuit type monostable-bistable transition logic element (MOBILE) circuit that uses resonant tunneling diodes (RTDs) and can prevent a malfunction caused by low peak-to-valley current ratio (PVCR) characteristics of the RTD includes an input data conversion circuit and an inverting F/F circuit. The input data conversion circuit receives input data and converts a logic level of the input data according to a logic level of output data of the MOBILE circuit. The inverting F/F circuit inverts a logic level of data output from the input data conversion circuit and outputs the output data. Accordingly, even when a logic level of input data changes from LOW to HIGH, the logic level of output data can be maintained HIGH in the inverting F/F type MOBILE circuit constructed using silicon semiconductor based RTDs with a small PVCR. Therefore, it is possible to enhance the performance of the inverting F/F circuit type MOBILE circuit.

Abstract translation: 使用谐振隧道二极管（RTD）的反相触发器（F / F）电路型单稳态双稳态转换逻辑元件（MOBILE）电路，并且可以防止由低峰值电流比（PVCR）特性引起的故障 RTD包括输入数据转换电路和反相F / F电路。 输入数据转换电路根据MOBILE电路的输出数据的逻辑电平接收输入数据并转换输入数据的逻辑电平。 反相F / F电路将从输入数据转换电路输出的数据的逻辑电平反相并输出输出数据。 因此，即使当输入数据的逻辑电平从低电平变为高电平时，在使用具有小PVCR的基于硅半导体的RTD构成的反相F / F型移动电路中，输出数据的逻辑电平也可以维持为高。 因此，可以提高反相F / F电路型MOBILE电路的性能。

公开(公告)号：US06780702B2

公开(公告)日：2004-08-24

申请号：US10271246

申请日：2002-10-15

Applicant: Myoung Hoon Yoon ,  Kyoung Hoon Yang

Inventor： Myoung Hoon Yoon ,  Kyoung Hoon Yang

IPC: H01L218249

CPC classification number: H01L29/66318 ,  H01L21/30612 ,  H01L29/0657 ,  H01L29/7371

Abstract: When InP DHBTs are located in parallel to a crystallographical direction of , there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general , there exists the limitation in reducing base-collector parasitic capacitance only by collector over-etching technique due to poor lateral-etching characteristic of the InP collector. To overcome such a problem mentioned above and improve device performance, the present invention provides a method of reducing parasitic capacitance using underneath crystallographically selective wet etching, thereby providing a self-alignable, structurally stable device.

Abstract translation: 当InP DHBT平行于<011>的晶体学方向时，在诸如可靠性的器件特性方面存在若干优点。 但是，在平行于一般<011>的方向的情况下，由于InP集电极的横向蚀刻特性差，存在仅通过集电极过蚀刻技术来减小集电极的寄生电容的限制。为了克服这种问题 提高了器件性能，本发明提供了一种使用晶体选择性湿蚀刻下降寄生电容的方法，从而提供了可自对准的结构稳定的器件。