公开(公告)号：US5673276A

公开(公告)日：1997-09-30

申请号：US716559

申请日：1996-02-05

申请人： Najmi Taher Jarwala ,  Chi Wang Yau

发明人： Najmi Taher Jarwala ,  Chi Wang Yau

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66 ,  H04B17/00

CPC分类号： G01R31/318558 ,  G01R31/318513 ,  G01R31/318536

摘要： A multi-chip module (10), having n semiconductor chips 14.sub.1 -14.sub.n, each chip having a Boundary-Scan architecture, is rendered Boundary-Scan-compliant both as a circuit board and as a macro-device by the addition of a bypass circuit (36, 36' and 36"). During selected intervals when the module (10) is to be Boundary-Scan-compliant as a macro-device, the bypass circuit operates to bypass the Test Data Input (18) to the Test Data Output (34) of each of n-1 chips. During other than the selected intervals, the bypass circuit allows test information applied to the Test Data Input of each of the chips to be shifted through the chip and to appear at its Test Data Output to facilitate Boundary-Scan compliance of the module as a circuit board.

摘要翻译： 具有n个半导体芯片141-14n的每个芯片具有边界扫描结构的多芯片模块（10）通过添加旁路被作为电路板和作为宏器件的边界扫描兼容 电路（36,36'和36“）。 在模块（10）作为宏器件符合边界扫描的选择间隔期间，旁路电路操作以将测试数据输入（18）旁路到n-1的测试数据输出（34） 筹码 在所选择的间隔之外，旁路电路允许应用于每个芯片的测试数据输入的测试信息通过芯片移位并出现在其测试数据输出端，以便于模块作为电路的边界扫描一致性 板。