公开(公告)号：US20130179854A1

公开(公告)日：2013-07-11

申请号：US13478040

申请日：2012-05-22

申请人： Naohito KOJIMA

发明人： Naohito KOJIMA

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F2217/78

摘要： According to one embodiment, a design apparatus includes a voltage drop analyzer, an improvement calculator, first and second cell replacing modules, and an outputting module. The voltage drop analyzer specifies a peak voltage drop point based on a cell library and design data. The cell library includes information on first and cell groups. The first cell replacing module changes the design data. The improvement calculator calculates a timing improvement. The second cell replacing module extracts at least one cell from second cell group in a target device corresponding to the design data changed by the first cell replacing module as a replacement candidate cell, based on the timing improvement, and changes the design data changed by the first cell replacing module. The outputting module outputs the design data changed by the second cell replacing module.

摘要翻译： 根据一个实施例，设计装置包括电压降分析器，改进计算器，第一和第二单元替换模块以及输出模块。 电压降分析仪根据单元库和设计数据指定峰值电压降点。 细胞库包括关于第一和细胞组的信息。 第一个电池更换模块会更改设计数据。 改进计算器计算时间改进。 第二单元更换模块基于时序改进，从与第一单元替换模块改变的设计数据相对应的目标设备中的第二单元组中提取至少一个单元，并且改变由 第一个电池更换模块。 输出模块输出由第二单元更换模块改变的设计数据。

公开(公告)号：US20070235766A1

公开(公告)日：2007-10-11

申请号：US11763432

申请日：2007-06-14

申请人： Naohito Kojima ,  Fumihiro Minami ,  Kimiyoshi Usami

发明人： Naohito Kojima ,  Fumihiro Minami ,  Kimiyoshi Usami

IPC分类号： H01L27/10 ,  G06F17/50 ,  H01L21/82

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

摘要翻译： 半导体集成电路包括布置在基板上的功能块，与功能块的第一侧相邻布置的第一缓冲单元，与邻近功能块第一侧相邻的第二侧布置的第二缓冲单元，以及信号 连接第一缓冲单元和第二缓冲单元的布线相对于第一侧和第二侧倾斜地越过功能块。

公开(公告)号：US07075336B2

公开(公告)日：2006-07-11

申请号：US10184425

申请日：2002-06-28

申请人： Naohito Kojima ,  Fumihiro Minami ,  Masami Murakata ,  Takashi Ishioka

发明人： Naohito Kojima ,  Fumihiro Minami ,  Masami Murakata ,  Takashi Ishioka

IPC分类号： H03K19/00 ,  H03K19/096 ,  G06F9/45 ,  G06F17/50 ,  G06F1/12

CPC分类号： G06F17/5045 ,  G06F1/10

摘要： A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

公开(公告)号：US06510542B1

公开(公告)日：2003-01-21

申请号：US09416200

申请日：1999-10-08

申请人： Naohito Kojima

发明人： Naohito Kojima

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A repeater insertion method is described which allows for repeater cell insertion into two or more fanout nets. Repeater cell location is determined such that at any given point, the interval capacitance between any two repeater cell nodes is no greater than a predetermined amount. Furthermore, the method allows for successful “back-annotation” into synthesis or layout software without the need to add new input/output pins to the module definition. Additionally, the method allows for repeater cell insertion using two or more sizes of repeater cells. Finally, the method described considers the “slack” of each fanout, and makes the signal delay from the source to the most critical fanout shorter than the result of usual repeater insertion methods.

摘要翻译： 描述了一种中继器插入方法，其允许中继器小区插入两个或更多扇出网。 确定中继器单元位置，使得在任何给定点处，任何两个中继器单元节点之间的间隔电容不大于预定量。 此外，该方法允许成功的“反向注释”到合成或布局软件中，而不需要向模块定义添加新的输入/输出引脚。 另外，该方法允许使用两个或更多个大小的中继器单元的中继器单元插入。 最后，所描述的方法考虑到每个扇出的“松弛”，并且使得从源到最关键的扇出的信号延迟比通常的中继器插入方法的结果短。

公开(公告)号：US5764531A

公开(公告)日：1998-06-09

申请号：US616991

申请日：1996-03-14

申请人： Naohito Kojima ,  Masaaki Yamada

发明人： Naohito Kojima ,  Masaaki Yamada

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A sizing apparatus for active devices of an integrated circuit has a storage unit for storing information about connections between the active devices and a delay constraint, a size initializing unit for initializing a size of the active device to a minimum value, an electric current consumption change rate arithmetic unit for calculating a change rate of an electric current or power consumption when the size is increased, a delay calculating unit for calculating a maximum signal delay by analyzing a timing on the basis of the connecting formation, a delay constraint judging unit for judging whether or not a maximum signal delay satisfies the delay constraint, a critical path extracting unit for extracting a critical path from paths that do not satisfy the delay constraint, a delay improvement arithmetic unit for calculating an improvement rate of the signal delay of the critical path with respect to a variation quantity of the electric current or power consumption when increasing the size of the active device, a selecting unit for selecting the active device having the maximum improvement rate and a control unit for selecting a minimum change rate of the electric current or power consumption and making the delay calculating unit calculate a signal delay when increasing the size of the active device in accordance with the selected change rate.

摘要翻译： 用于集成电路的有源器件的尺寸设备具有存储单元，用于存储关于有源器件之间的连接的信息和延迟约束，用于将有源器件的尺寸初始化为最小值的尺寸初始化单元，电流消耗变化 速率算术单元，用于计算大小增大时的电流或功耗的变化率;延迟计算单元，用于通过基于连接形成分析定时来计算最大信号延迟;延迟约束判断单元，用于判断 确定最大信号延迟是否满足延迟约束;关键路径提取单元，用于从不满足延迟约束的路径提取关键路径;延迟改善运算单元，用于计算关键路径的信号延迟的改善率 相对于增加时的电流或功耗的变化量 有源器件的尺寸，用于选择具有最大改善率的有源器件的选择单元和用于选择电流或功耗的最小变化率的控制单元，并且使延迟计算单元在增大尺寸时计算信号延迟 根据所选择的变化率来激活有源器件。

公开(公告)号：US08026537B2

公开(公告)日：2011-09-27

申请号：US11763432

申请日：2007-06-14

申请人： Naohito Kojima ,  Fumihiro Minami ,  Kimiyoshi Usami

发明人： Naohito Kojima ,  Fumihiro Minami ,  Kimiyoshi Usami

IPC分类号： H01L27/10

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

摘要翻译： 半导体集成电路包括布置在基板上的功能块，与功能块的第一侧相邻布置的第一缓冲单元，与邻近功能块第一侧相邻的第二侧布置的第二缓冲单元，以及信号 连接第一缓冲单元和第二缓冲单元的布线相对于第一侧和第二侧倾斜地越过功能块。