利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

626 条记录 (耗时 0.025 秒)

    Area efficient traffic generator
    2.
    发明授权
    Area efficient traffic generator 有权

    公开(公告)号：US11973670B2

    公开(公告)日：2024-04-30

    申请号：US17514235

    申请日：2021-10-29

    申请人： Accedian Networks Inc.

    发明人： Steve Rochon

    IPC分类号： G06F11/00 ,  G06F11/30 ,  G06F11/34 ,  G06F13/362 ,  H04L43/026 ,  H04L43/50 ,  H04L47/283 ,  H04L43/08

    CPC分类号： H04L43/026 ,  G06F11/3003 ,  G06F11/3006 ,  G06F11/3452 ,  G06F11/349 ,  G06F13/3625 ,  H04L43/50 ,  H04L47/283 ,  H04L43/08

    摘要： A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

    AUTOMATIC BUFFER POOL PAGE FIX PRIORITIZATION FOR DATABASE TUNING
    4.
    发明公开
    AUTOMATIC BUFFER POOL PAGE FIX PRIORITIZATION FOR DATABASE TUNING 审中-公开

    公开(公告)号：US20230315697A1

    公开(公告)日：2023-10-05

    申请号：US17657347

    申请日：2022-03-30

    申请人： BMC Software, Inc.

    发明人： Donnell W. Roach

    IPC分类号： G06F16/21 ,  G06F16/2455 ,  G06F16/2457 ,  G06F11/34

    CPC分类号： G06F16/21 ,  G06F16/24552 ,  G06F16/24578 ,  G06F11/3485 ,  G06F11/349

    摘要： For each database subsystem in a plurality of database subsystems running in a logical partition (LPAR), the systems and techniques include collecting data from buffer pools on a periodic interval, monitoring real storage availability on the LPAR, calculating an input/output (I/O) intensity score for each buffer pool for the periodic interval, ranking the buffer pools based on the I/O intensity score, calculating a cumulative I/O intensity score for each buffer pool across a cycle of multiple periodic intervals, ranking the buffer pools based on the cumulative I/O intensity score, and selecting a buffer pool candidate for page fixing. The buffer pool candidate for page fixing is a highest-ranked buffer pool from the plurality of buffer pools during the cycle based on the cumulative I/O intensity score that satisfies the real storage availability on the LPAR.

    Tracing activity from multiple components of a device
    6.
    发明授权
    Tracing activity from multiple components of a device 有权

    公开(公告)号：US11675686B2

    公开(公告)日：2023-06-13

    申请号：US17445550

    申请日：2021-08-20

    申请人： Graphcore Limited

    发明人： Daniel John Pelham Wilkinson ,  Graham Bernard Cunningham

    IPC分类号： G06F11/34 ,  G06F13/40

    CPC分类号： G06F11/349 ,  G06F13/4068

    摘要： A device comprising: a bus forming a ring path for circulation of one or more data packets around the bus, wherein the one or more data packets comprises a trace report packet for collecting trace data from a plurality of components attached to the bus, wherein the bus is configured to repeatedly circulate the trace report packet with a fixed time period taken for each circulation of the ring path performed by the trace report packet; and the plurality of components, each of which comprises circuitry configured to, upon reception of the trace report packet at the respective component, insert one or more items of the trace data that have been obtained by the respective component.

    AREA EFFICIENT TRAFFIC GENERATOR
    7.
    发明申请
    AREA EFFICIENT TRAFFIC GENERATOR 审中-公开

    公开(公告)号：US20190116099A1

    公开(公告)日：2019-04-18

    申请号：US16229280

    申请日：2018-12-21

    申请人： Accedian Networks Inc.

    发明人： Steve Rochon

    IPC分类号： H04L12/26 ,  H04L12/841 ,  G06F11/34 ,  G06F13/362 ,  G06F11/30

    CPC分类号： H04L43/026 ,  G06F11/3006 ,  G06F11/3452 ,  G06F11/349 ,  G06F13/3625 ,  H04L43/08 ,  H04L43/50 ,  H04L47/283

    摘要： A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

    INPUT AND OUTPUT RECORDING DEVICE AND METHOD, CPU AND DATA READ AND WRITE OPERATION METHOD THEREOF
    9.
    发明申请
    INPUT AND OUTPUT RECORDING DEVICE AND METHOD, CPU AND DATA READ AND WRITE OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20180239686A1

    公开(公告)日：2018-08-23

    申请号：US15895686

    申请日：2018-02-13

    申请人： TSINGHUA UNIVERSITY

    发明人： Leibo LIU ,  Ao LUO ,  Shaojun WEI

    IPC分类号： G06F11/34

    CPC分类号： G06F11/3485 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/349 ,  G06F21/566 ,  G06F21/71

    摘要： The disclosure provides an input and output recording device and method, CPU and data read and write operation method thereof. The input and output recording device is provided between a central processor CPU and a peripheral, and is configured to record data read and write operations between the CPU and the peripheral, wherein the data read and write operations comprise a data read and write operation initiated by the peripheral and a data read and write operation initiated by the CPU; the input and output recording device is further configured to request the CPU to process the data read and write operation initiated by the peripheral, and upon receiving an instruction sent by the CPU, send a data packet of the data read and write operation initiated by the peripheral to the CPU. The disclosure can accurately record the data read and write operation between the CPU and the peripheral, so as to eliminate the influence of uncertainty caused by the asynchronous data read and write operations initiated by the peripherals, and provide a basis for the input and output security checking of the CPU.

    System on chip and corresponding monitoring method
    10.
    发明授权
    System on chip and corresponding monitoring method 有权

    公开(公告)号：US09952963B2

    公开(公告)日：2018-04-24

    申请号：US14078960

    申请日：2013-11-13

    申请人： HUAWEI TECHNOLOGIES CO., LTD.

    发明人： Chenglei Mou ,  Qi Han

    IPC分类号： G06F13/362 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

    CPC分类号： G06F11/364 ,  G06F11/3027 ,  G06F11/3065 ,  G06F11/348 ,  G06F11/349 ,  G06F11/3648 ,  G06F2213/0038

    摘要： The present invention relates to aSoC, which includes a master device, a slave device, a high-speed bus, and a monitoring apparatus. The master device is connected to a first port of the high-speed bus, and the slave device is connected to a second port of the high-speed bus, so that the master device is capable of accessing the slave device. The monitoring apparatus is arranged between the first port of the high-speed bus and the master device, and/or between the second port of the high-speed bus and the slave device, and configured to record, based on a high-speed bus communication protocol, state information of each command that passes through the first port and/or the second port, and when state information of a command indicates that an operation of the command is in a timeout state, report an interrupt to locate a faulty node on the high-speed bus.