公开(公告)号：US07567105B2

公开(公告)日：2009-07-28

申请号：US11317972

申请日：2005-12-23

申请人： Narasimhan R. Trichy ,  Wayne Tien-Feng Chen

发明人： Narasimhan R. Trichy ,  Wayne Tien-Feng Chen

IPC分类号： H03K3/00

CPC分类号： H04L25/0276 ,  G06F13/4072 ,  H04L12/40013 ,  H04L12/40032 ,  H04L2012/40215 ,  H04L2012/40273

摘要： A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a two wire line by a predetermined amount and amplifying the signal by the same predetermined amount. The front-end amplifier generates the common-mode voltage of the input signal for a reference generator that determines the logic level of the incoming signal and subtracts a bandgap voltage reference from the common-mode voltage. A comparator compares the difference between the output of the front-end amplifier and the resultant signal generated by the reference generator to generate an output signal for the receiver. This CAN receiver architecture is faster than conventional designs and possesses an improved common-mode rejection, while operating over a wide input common mode range.

摘要翻译： 本文公开了提供比常规设计更好的抵抗EMI干扰的CAN接收器架构设计。 该CAN接收机包括连接到前端放大器的分压器网络，用于将来自两条线的输入信号除以预定量，并以相同的预定量放大信号。 前端放大器产生用于参考发生器的输入信号的共模电压，其确定输入信号的逻辑电平，并从共模电压中减去带隙电压基准。 比较器比较前端放大器的输出与由参考发生器产生的合成信号之间的差异，以产生接收机的输出信号。 该CAN接收器架构比传统设计更快，并且在宽输入共模范围内工作时具有改进的共模抑制。

公开(公告)号：US07274916B2

公开(公告)日：2007-09-25

申请号：US10898272

申请日：2004-07-23

申请人： Mohammad A. Al-Shyoukh ,  Narasimhan R. Trichy

发明人： Mohammad A. Al-Shyoukh ,  Narasimhan R. Trichy

IPC分类号： H04B1/26 ,  H04B1/28

CPC分类号： H03F3/45076

摘要： A differential signal receiver and method is disclosed. One embodiment relates to a receiver for receiving a differential signal. The receiver includes a first voltage-to-current converter that converts the voltage received at a first input to a first current, and a second voltage-to-current converter that converts a voltage signal received at a second input to a second current. A current subtractor provides a difference current of the first and second currents that is indicative of the differential signal.

摘要翻译： 公开了一种差分信号接收机和方法。 一个实施例涉及用于接收差分信号的接收机。 接收器包括将在第一输入处接收的电压转换为第一电流的第一电压 - 电流转换器，以及将在第二输入处接收的电压信号转换为第二电流的第二电压 - 电流转换器。 电流减法器提供表示差分信号的第一和第二电流的差分电流。

公开(公告)号：US07236034B2

公开(公告)日：2007-06-26

申请号：US10901833

申请日：2004-07-27

申请人： Wayne T. Chen ,  Narasimhan R. Trichy

发明人： Wayne T. Chen ,  Narasimhan R. Trichy

IPC分类号： H03H11/06

CPC分类号： H03K19/00323 ,  H03K2005/00097 ,  H03K2005/00123 ,  H04L25/0272

摘要： The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having an input coupled to an output of the first comparator; a second flip flop having an input coupled to an output of the second comparator; a counter having inputs coupled to the first and second flip flops; and a delay device controlled by an output of the counter, wherein the delay device provides a pull down control signal that is delayed relative to a pull up control signal.

摘要翻译： 匹配上拉和下拉器件的自校正方案包括：用于将共模信号与高参考极限进行比较的第一比较器; 第二比较器，用于将共模信号与低参考极限进行比较; 第一触发器，其具有耦合到所述第一比较器的输出的输入; 第二触发器，具有耦合到第二比较器的输出的输入; 具有耦合到第一和第二触发器的输入的计数器; 以及由计数器的输出控制的延迟装置，其中延迟装置提供相对于上拉控制信号延迟的下拉控制信号。