公开(公告)号：US08283948B2

公开(公告)日：2012-10-09

申请号：US12757773

申请日：2010-04-09

Applicant: Neeraj Shrivastava

Inventor： Neeraj Shrivastava

IPC: H03K5/00

CPC classification number: G11C27/024

Abstract: A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals.

Abstract translation: 提供采样保持（S / H）电路。 S / H电路通常包括采样开关，采样电容器和校正网络。 接收模拟输入信号的采样开关由定时信号启动和去激活。 采样电容器在采样节点处耦合到采样开关，以便当采样开关被致动时接收模拟输入信号，并且当采样开关被去激活时存储模拟输入信号的电压。 校正网络具有至少一行变容二极管单元，使得每个变容二极管单元耦合到采样节点，并且其中该行中的每个变电位单元接收参考电压。 此外，每个变容二极管单元接收多个控制信号中的至少一个。

公开(公告)号：US20090184853A1

公开(公告)日：2009-07-23

申请号：US12337658

申请日：2008-12-18

Applicant: Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

Inventor： Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/129 ,  H03M1/069 ,  H03M1/164

Abstract: An aspect of the present invention avoids an amplifier of an analog to digital converter (ADC) from entering a saturation region. In an embodiment, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.

Abstract translation: 本发明的一个方面避免了模数转换器（ADC）的放大器进入饱和区域。 在一个实施例中，将ADC的输入信号的样本与ADC的上限和下限满量程电平进行比较。 如果检测到输入过载，则在输入过载的持续时间内，ADC输入级放大器的输入被强制为零，从而防止输入过饱和。 输入过载条件直接发送到ADC的输出数字模块，该输出数字模块根据输入过载信号是否超过上限或下限，提供相当于上限或下限满量程级别的输出数字代码。 因此可以将ADC的输入过载恢复时间最小化。

公开(公告)号：US20100259302A1

公开(公告)日：2010-10-14

申请号：US12757773

申请日：2010-04-09

Applicant: Neeraj Shrivastava

Inventor： Neeraj Shrivastava

IPC: G11C27/02

CPC classification number: G11C27/024

Abstract: A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals.

Abstract translation: 提供采样保持（S / H）电路。 S / H电路通常包括采样开关，采样电容器和校正网络。 接收模拟输入信号的采样开关由定时信号启动和去激活。 采样电容器在采样节点处耦合到采样开关，以便当采样开关被致动时接收模拟输入信号，并且当采样开关被去激活时存储模拟输入信号的电压。 校正网络具有至少一行变容二极管单元，使得每个变容二极管单元耦合到采样节点，并且其中该行中的每个变电位单元接收参考电压。 此外，每个变容二极管单元接收多个控制信号中的至少一个。

公开(公告)号：US07786909B2

公开(公告)日：2010-08-31

申请号：US12337658

申请日：2008-12-18

Applicant: Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

Inventor： Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

IPC: H03M1/06

CPC classification number: H03M1/129 ,  H03M1/069 ,  H03M1/164

Abstract: With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.

Abstract translation: 使用高速模数转换器（ADC）时，当输入超过ADC的输入范围时，ADC内部的器件可能会进入饱和区，从而导致错误。 这里，将ADC的输入信号的样本与ADC的上限和下限满量程电平进行比较。 如果检测到输入过载，则在输入过载的持续时间内，ADC输入级放大器的输入被强制为零，从而防止输入过饱和。 输入过载条件直接发送到ADC的输出数字模块，根据输入过载信号是否超过上限或下限，提供与上限或下限满量程电平相当的输出数字代码。 因此可以将ADC的输入过载恢复时间最小化。