公开(公告)号：US11669831B2

公开(公告)日：2023-06-06

申请号：US17224300

申请日：2021-04-07

Applicant: Miles Paschini ,  Nitin Agarwal

Inventor： Miles Paschini ,  Nitin Agarwal

IPC: G06Q20/36 ,  H04L9/06 ,  G06Q20/40

CPC classification number: G06Q20/3672 ,  G06Q20/3674 ,  G06Q20/3678 ,  G06Q20/4016 ,  H04L9/0637

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

公开(公告)号：US08581634B2

公开(公告)日：2013-11-12

申请号：US12763945

申请日：2010-04-20

Applicant: Nitin Agarwal ,  Visvesvaraya A. Pentakota

Inventor： Nitin Agarwal ,  Visvesvaraya A. Pentakota

IPC: G11C27/02

CPC classification number: H03K19/018528 ,  G11C27/024

Abstract: Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.

Abstract translation: 传统上，模数转换器（ADC）的输入源跟随缓冲器缺乏足够高的线性度。 这是由于源极跟随缓冲器必须通过向容性负载提供信号电流来驱动外部电容性负载。 这里提供了缓冲器，其包括源极跟随器缓冲器和其它偏置电路（其提供信号电流）。 因此，输入电路（即，输入缓冲器）的整体线性度得到改善。

公开(公告)号：US08310290B2

公开(公告)日：2012-11-13

申请号：US12938155

申请日：2010-11-02

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03L7/06

CPC classification number: H03L7/0816 ,  H03M1/0836 ,  H03M1/145 ,  H03M1/164 ,  H03M1/44

Abstract: In conventional analog-to-digital converter (ADC) systems, jitter can be a problem because of delay circuits within the sample signal path. Here, an ADC system is provided with a modified delay locked loop (DLL), namely having a variable delay and a fixed delay. The modification to the delay line of DLL enables the removal of delay circuits from the sample path, improve the overall signal to noise ration (SNR).

Abstract translation: 在传统的模数转换器（ADC）系统中，由于采样信号路径内的延迟电路，抖动可能是一个问题。 这里，ADC系统具有修改的延迟锁定环（DLL），即具有可变延迟和固定延迟。 对DLL的延迟线的修改使得能够从采样路径去除延迟电路，从而提高整体信噪比（SNR）。

公开(公告)号：US20110313898A1

公开(公告)日：2011-12-22

申请号：US12819774

申请日：2010-06-21

Applicant: Nitesh Singhal ,  Parijat Sinha ,  Nitin Agarwal ,  Muthukumar Murugesan

Inventor： Nitesh Singhal ,  Parijat Sinha ,  Nitin Agarwal ,  Muthukumar Murugesan

IPC: G06Q20/00 ,  G06F21/20 ,  G06Q40/00 ,  G06Q10/00 ,  G06Q30/00

CPC classification number: G06Q20/409 ,  G06F21/34 ,  G06Q20/12 ,  G06Q20/40 ,  G06Q30/06 ,  G06Q30/0609 ,  G06Q30/0635 ,  G06Q40/12 ,  H04L63/083

Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.

Abstract translation: 根据一个或多个实施例的用于促进网络上的电子商务的系统和方法包括通过网络经由发行者设备经由用户设备和支付媒体的发行者与用户通信，所述支付媒体被发送给用户 由发行者通过网络接收用户指令以将支付媒体链接到与用户相关的用户帐户，通过网络提示用户输入仅由发行者和用户知道的安全密码，从安全密码接收安全密码 用户通过安全协议验证支付媒体是否由用户拥有，返回与用户有关的支付媒体验证的响应，以及存储支付媒体验证信息。

公开(公告)号：US07804328B2

公开(公告)日：2010-09-28

申请号：US12199804

申请日：2008-08-28

Applicant: Visvesvaraya Appala Pentakota ,  Nitin Agarwal

Inventor： Visvesvaraya Appala Pentakota ,  Nitin Agarwal

IPC: H03K17/16 ,  H03B1/00

CPC classification number: H03M1/124 ,  H03F3/505 ,  H03F2200/312 ,  H03F2203/5031

Abstract: A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.

Abstract translation: 根据本发明的一方面提供的源极跟随器或射极跟随器缓冲器包括连接在输入路径和由形成连接到缓冲器的输出的级联电流源的一对晶体管的结的形成的节点之间的电容器。 电容器将输入信号电流直接传递到连接到缓冲器输出的开关负载，并且极少的信号相关电流流过接收输入信号的晶体管。 结果，由于接收输入信号的晶体管的跨导的信号相关调制（变化）引起的输入 - 输出非线性被最小化。 当结合在开关电容器模数转换器中时，缓冲器便于更准确地产生代表输入信号的数字代码。

公开(公告)号：US20090184853A1

公开(公告)日：2009-07-23

申请号：US12337658

申请日：2008-12-18

Applicant: Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

Inventor： Anand Hariraj Udupa ,  Neeraj Shrivastava ,  Nitin Agarwal

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/129 ,  H03M1/069 ,  H03M1/164

Abstract: An aspect of the present invention avoids an amplifier of an analog to digital converter (ADC) from entering a saturation region. In an embodiment, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.

Abstract translation: 本发明的一个方面避免了模数转换器（ADC）的放大器进入饱和区域。 在一个实施例中，将ADC的输入信号的样本与ADC的上限和下限满量程电平进行比较。 如果检测到输入过载，则在输入过载的持续时间内，ADC输入级放大器的输入被强制为零，从而防止输入过饱和。 输入过载条件直接发送到ADC的输出数字模块，该输出数字模块根据输入过载信号是否超过上限或下限，提供相当于上限或下限满量程级别的输出数字代码。 因此可以将ADC的输入过载恢复时间最小化。

公开(公告)号：US20080048899A1

公开(公告)日：2008-02-28

申请号：US11510259

申请日：2006-08-25

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03M3/00

CPC classification number: H03K7/08 ,  H03M1/661 ,  H03M1/822

Abstract: A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.

Abstract translation: 系统和方法产生具有可变占空比分辨率的脉宽调制信号。 硬件使用最小的硬件来将PWM占空比分辨率提高到0，从而可以获得最高可能的波形分辨率，包括正弦波。 本发明的实施例使用微控制器，W计数器除法，延迟电路，触发器和逻辑门。

公开(公告)号：US07286003B2

公开(公告)日：2007-10-23

申请号：US11209351

申请日：2005-08-22

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: G05F1/10

CPC classification number: G05F3/242 ,  H03K3/356113 ,  H03K17/102

Abstract: An improved on-chip voltage regulator providing improved reliability by eliminating voltage stresses on critical components, comprising, a reference-signal generating block providing a first-order temperature-compensated voltage-reference signal and a first-order temperature-compensated current-reference signal, an operational-amplifier block providing a regulated voltage, connected to the outputs of said reference signal generating block; a standby protection block receiving an external signal for enabling/disabling said reference-signal generating block and said operational-amplifier block, and; a protection voltage block connected to all said blocks; wherein critical elements of said blocks are connected such that voltage difference between any two terminals is always less than the break down voltage of said critical element.

Abstract translation: 一种改进的片上稳压器，通过消除关键部件上的电压应力来提供改进的可靠性，包括：提供一阶温度补偿电压参考信号的参考信号产生模块和一阶温度补偿电流参考信号 提供连接到所述参考信号产生块的输出的调节电压的运算放大器块; 接收外部信号的待机保护块，用于启用/禁用所述参考信号产生块和所述运算放大器块; 连接到所有所述块的保护电压块; 其中所述块的关键元件被连接，使得任何两个端子之间的电压差始终小于所述临界元件的击穿电压。

公开(公告)号：US20070013569A1

公开(公告)日：2007-01-18

申请号：US11160859

申请日：2005-07-13

Applicant: Anand Udupa ,  Vikas Sinha ,  Nitin Agarwal ,  Visvesvaraya PENTAKOTA ,  Sandeep Oswal

Inventor： Anand Udupa ,  Vikas Sinha ,  Nitin Agarwal ,  Visvesvaraya PENTAKOTA ,  Sandeep Oswal

IPC: H03M1/12

CPC classification number: H03M1/168

Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Abstract translation: 流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC， 减法器和放大）。 由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

公开(公告)号：US20210264408A1

公开(公告)日：2021-08-26

申请号：US17224300

申请日：2021-04-07

Applicant: Miles PASCHINI ,  Nitin AGARWAL

Inventor： Miles PASCHINI ,  Nitin AGARWAL

IPC: G06Q20/36 ,  H04L9/06 ,  G06Q20/40

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.