公开(公告)号：US20050097413A1

公开(公告)日：2005-05-05

申请号：US10795231

申请日：2004-03-09

申请人： Srivaths Ravi ,  Anand Raghunathan ,  Loganathan Lingappan ,  Srimat Chakradhar ,  Niraj Jha

发明人： Srivaths Ravi ,  Anand Raghunathan ,  Loganathan Lingappan ,  Srimat Chakradhar ,  Niraj Jha

IPC分类号： G01R31/28 ,  H01L20060101

CPC分类号： G06F11/263 ,  G01R31/318547

摘要： An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.

摘要翻译： 一种集成电路，包括至少一个系统级解压缩器和至少与核心级解压缩器相关联的第一硬件块。 系统级解压缩器能够对接收到的压缩测试数据执行系统级解压缩，形成部分解压缩的测试数据。 核心级解压缩器能够执行部分解压缩测试数据的核心级解压缩。

公开(公告)号：US20070022395A1

公开(公告)日：2007-01-25

申请号：US11278182

申请日：2006-03-31

申请人： Srivaths Ravi ,  Anand Raghunathan ,  Lin Zhong ,  Niraj Jha

发明人： Srivaths Ravi ,  Anand Raghunathan ,  Lin Zhong ,  Niraj Jha

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/78

摘要： A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.

摘要翻译： 一种用于估计设计中的电子电路的功耗的方法，其采用循环精确功能描述（CAFD），其有利地提供通过RTL功率估计获得的精度，其具有高级方法的速度和速度。

公开(公告)号：US06463560B1

公开(公告)日：2002-10-08

申请号：US09338338

申请日：1999-06-23

申请人： Sudipta Bhawmik ,  Indradeep Ghosh ,  Niraj Jha

发明人： Sudipta Bhawmik ,  Indradeep Ghosh ,  Niraj Jha

IPC分类号： G01R3187

CPC分类号： G01R31/3187

摘要： A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.

摘要翻译： 一种用于使用BIST方案测试控制器数据路径RTL电路的方法，而不对电路施加任何主要的设计限制。 使用状态机提取程序从控制器网表中提取状态表。 然后选择电路中未经测试的RTL元件/模块，并从控制器/数据通路中提取电路的测试控制和数据流（TCDF）。 一旦为所选择的RTL元素提取TCDF，就执行符号可测试性分析（STA）以获得尽可能多的未经测试的数据路径元素的测试环境。 记录和/或存储特定测试环境所需的这些测试多路复用器的选择信号的控制器输入序列。 从所存储的输入序列合成BIST控制器，并且使用由此确定的BIST架构将电路与BIST组件集成。