公开(公告)号：US08890594B1

公开(公告)日：2014-11-18

申请号：US13938244

申请日：2013-07-10

Applicant: Surendra Kumar Tadi ,  Nitin Kumar Jaiswal

Inventor： Surendra Kumar Tadi ,  Nitin Kumar Jaiswal

IPC: H03K3/36 ,  H03K3/037

CPC classification number: H03K3/0375

Abstract: A system for synchronizing a functional reset between first and second clock domains that operate on first and second clock signals, respectively. The system includes first, second and third synchronizer flip-flops that operate on the second clock signal. The first synchronizer flip-flop receives a functional reset signal generated by the first clock domain at its reset terminal and generates a low output signal. The low output signal causes the second synchronizer flip-flop and subsequently the third synchronizer flip-flop to generate low output signals at positive edges of the second clock signal. The low output signal generated by the third synchronizer flip-flop is used to reset the second clock domain.

Abstract translation: 一种用于在第一和第二时钟域之间分别对第一和第二时钟信号进行功能复位同步的系统。 该系统包括在第二时钟信号上工作的第一，第二和第三同步器触发器。 第一同步触发器在其复位端接收由第一时钟域产生的功能复位信号，并产生低输出信号。 低输出信号引起第二同步触发器，随后第三同步触发器在第二时钟信号的正边沿产生低输出信号。 由第三同步触发器产生的低输出信号用于复位第二时钟域。