公开(公告)号：US5214609A

公开(公告)日：1993-05-25

申请号：US751768

申请日：1991-08-29

申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Nobuaki Hiraga

发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Nobuaki Hiraga

IPC分类号： G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/18 ,  G11C11/407 ,  G11C11/409 ,  G11C16/06

CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C8/18

摘要： In the semiconductor integrated circuit, the data delay circuit and data latch circuit are connected between the sense amplifier circuit and the output buffer circuit. A pulse signal for controlling the output buffer is first generated according to a pulse output signal of the address change detection circuit, and then a latch signal which permits output data of the data detection circuit obtained before the change of the address input signal to be latched by the data latch circuit for a preset period of time is generated. Next, a delay signal is generated which sets the delay time of the data delay circuit to be short in a case where data detected by the data detection circuit is not output from the output buffer circuit, and sets the delay time of the data delay circuit to be long in a case where data is output from the output buffer circuit. Generation of the delay signal is interrupted after the pulse signal of the address change detection circuit is interrupted. As a result, the power source variation at the time of output data change or erroneous operation due to noise input from the exterior can be prevented. Further, the driving ability of the output buffer transistor can be set to a large value so that a highly reliable semiconductor integrated circuit in which the operation margin of the integrated circuit with respect to the power source variation and noise can be made large while keeping the data readout speed high can be obtained.