公开(公告)号：US20050071413A1

公开(公告)日：2005-03-31

申请号：US10841261

申请日：2004-05-07

申请人： Michael Schulte ,  Pablo Balzola ,  C. Glossner

发明人： Michael Schulte ,  Pablo Balzola ,  C. Glossner

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/544 ,  G06F9/302 ,  G06F9/38

CPC分类号： G06F9/30101 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3893

摘要： A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

摘要翻译： 具有减少单元的处理器，其将m个输入操作数加上累加器值相加，并且可以在每次添加之后饱和选项或围绕每次添加的结果进行包围。 缩小单元还允许通过简单地反转输入操作数的位并将多个还原加法器中的每一个设置为一个，从累加器值中减去m个输入操作数。 还原单元可以与m个并行乘法器一起使用，以便通过饱和或循环运算来快速执行点积和其他向量运算。

公开(公告)号：US20050060359A1

公开(公告)日：2005-03-17

申请号：US10892686

申请日：2004-07-16

申请人： Michael Schulte ,  Erdem Hokenek ,  Pablo Balzola ,  C. Glossner

发明人： Michael Schulte ,  Erdem Hokenek ,  Pablo Balzola ,  C. Glossner

IPC分类号： G06F7/499 ,  G06F7/50 ,  G06F7/507 ,  G06F7/38

CPC分类号： G06F7/507 ,  G06F7/49921

摘要： An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.

摘要翻译： 一种用于对至少第一和第二输入操作数执行算术运算的算术单元，每个输入操作数可分为第一部分和第二部分，例如各自不太重要和更重要的部分。 算术单元包括第一运算电路，第二运算电路，选择电路和饱和电路。 可以包括进位传播加法器的第一算术电路处理输入操作数的第一部分以产生至少一个临时和和进位输出。 可以包括双加法器和初步饱和检测器的第二运算电路处理输入操作数的第二部分以产生一个或多个临时和和多个饱和标志。 选择电路被配置为基于第一运算电路的进位输出来选择第二运算电路的一个或多个输出。 饱和电路具有耦合到第一算术电路和选择电路的对应输出的输入，并且被配置为产生算术运算的结果。

公开(公告)号：US20090193279A1

公开(公告)日：2009-07-30

申请号：US12362329

申请日：2009-01-29

申请人： Mayan MOUDGILL ,  Vitaly Kalashnikov ,  Murugappan Senthilvelan ,  Umesh Srikantiah ,  Tak-po Li ,  Pablo Balzola

发明人： Mayan MOUDGILL ,  Vitaly Kalashnikov ,  Murugappan Senthilvelan ,  Umesh Srikantiah ,  Tak-po Li ,  Pablo Balzola

IPC分类号： G06F1/08

CPC分类号： G06F9/526 ,  G06F9/52

摘要： A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

摘要翻译： 描述了一种用于向多个处理器提供至少一个值序列的方法。 在该方法中，来自一个或多个序列生成器的序列生成器与存储器位置相关联。 序列生成器被配置为生成至少一个值序列。 存储器位置的一个或多个读取访问由来自多个处理器的处理器启用。 响应于启用读取访问，序列生成器被执行，使得其从值序列返回到处理器的第一值。 在执行序列生成器之后，序列发生器被提前使得下一次访问从值序列生成第二个值。 第二个值依次在第一个值之后。

公开(公告)号：US08539188B2

公开(公告)日：2013-09-17

申请号：US12362329

申请日：2009-01-29

申请人： Mayan Moudgill ,  Vitaly Kalashnikov ,  Murugappan Senthilvelan ,  Umesh Srikantiah ,  Tak-po Li ,  Pablo Balzola

发明人： Mayan Moudgill ,  Vitaly Kalashnikov ,  Murugappan Senthilvelan ,  Umesh Srikantiah ,  Tak-po Li ,  Pablo Balzola

IPC分类号： G06F12/14

CPC分类号： G06F9/526 ,  G06F9/52

摘要： A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

摘要翻译： 描述了一种用于向多个处理器提供至少一个值序列的方法。 在该方法中，来自一个或多个序列生成器的序列生成器与存储器位置相关联。 序列生成器被配置为生成至少一个值序列。 存储器位置的一个或多个读取访问由来自多个处理器的处理器启用。 响应于启用读取访问，序列生成器被执行，使得其从值序列返回到处理器的第一值。 在执行序列生成器之后，序列发生器被提前使得下一次访问从值序列生成第二个值。 第二个值依次在第一个值之后。