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公开(公告)号：US5692014A
公开(公告)日：1997-11-25
申请号：US383381
申请日：1995-02-03
IPC分类号： H04L7/033 , H04L27/227 , H04L27/22 , H04L7/00
CPC分类号： H04L27/2273 , H04L7/0334
摘要： A high performance, low cost technique for carrier recovery and tracking of high rate demodulator (>200 Mbps to multi-gigabits per second) system is presented. The locally generated carrier is held in phase locked synchronism with the incoming modulated carrier through a carrier recovery scheme in which the modulated data is detected and subsampled using the bit synchronizing circuitry to provide a strobe signal for subsampling. The voltage levels of the subsampled data are analyzed to determine a phase error signal. The subsampled data are used to address a lookup table of error values stored in memory.
摘要翻译： 提出了一种用于载波恢复和高速率解调器跟踪（高达200 Mbps至每千兆位千兆位）的高性能，低成本技术。 本地生成的载波通过载波恢复方案与输入的调制载波保持同步，其中调制的数据被检测并且使用比特同步电路进行二次采样，以提供用于子采样的选通信号。 分析子采样数据的电压电平以确定相位误差信号。 子采样数据用于寻址存储在存储器中的错误值查找表。
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公开(公告)号：US5892798A
公开(公告)日：1999-04-06
申请号：US963363
申请日：1997-11-03
CPC分类号： H04L27/2014
摘要： A modulated clock MSK modulator that separately modulates a sinusoidal clock signal by square wave I and Q digital data signals prior to the I and Q data signals being modulated onto a carrier wave signal. Mixers or applicable biphase switches are utilized to impress the I and Q digital data signal information onto the clock signal by inverting or non-inverting the clock signal on separate I and Q data rails to create I and Q modulated clock signals separated in phase. The I channel data modulated clock signal and the Q channel data modulated clock signal are then separately applied to a conventional quadraphase modulator to be separately modulated onto a carrier wave signal, and the summed together to be transmitted.
摘要翻译： 调制时钟MSK调制器，在将I和Q数据信号调制到载波信号之前，通过方波I和Q数字数据信号分别调制正弦时钟信号。 混频器或适用的双相开关用于通过在单独的I和Q数据轨上反相或非反相时钟信号来将I和Q数字数据信号信息压印到时钟信号上，以产生分相的I和Q调制时钟信号。 然后将I信道数据调制时钟信号和Q信道数据调制时钟信号分别应用于传统的四图形调制器，以分别调制到载波信号上，并将其相加在一起传输。
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公开(公告)号：US5748679A
公开(公告)日：1998-05-05
申请号：US430570
申请日：1995-04-28
CPC分类号： H04L27/2014
摘要： A modulated clock MSK modulator that separately modulates a sinusoidal clock signal by square wave I and Q digital data signals prior to the I and Q data signals being modulated onto a carrier wave signal. Mixers or applicable biphase switches are utilized to impress the I and Q digital data signal information onto the clock signal by inverting or non-inverting the clock signal on separate I and Q data rails to create I and Q modulated clock signals separated in phase. The I channel data modulated clock signal and the Q channel data modulated clock signal are then separately applied to a conventional quadraphase modulator to be separately modulated onto a carrier wave signal, and the summed together to be transmitted.
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