公开(公告)号：US06157967A

公开(公告)日：2000-12-05

申请号：US1100

申请日：1997-12-30

申请人： Robert W. Horst ,  William Edward Baker ,  Linda Ellen Zalzala ,  William Patterson Bunton ,  Richard W. Cutts, Jr. ,  David J. Garcia ,  John C. Krause ,  Stephen G. Low ,  David Paul Sonnier ,  William Joel Watson ,  Patracia L. Whiteside

发明人： Robert W. Horst ,  William Edward Baker ,  Linda Ellen Zalzala ,  William Patterson Bunton ,  Richard W. Cutts, Jr. ,  David J. Garcia ,  John C. Krause ,  Stephen G. Low ,  David Paul Sonnier ,  William Joel Watson ,  Patracia L. Whiteside

IPC分类号： G06F11/00 ,  G06F15/173 ,  H04L1/16

CPC分类号： G06F15/17381

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。