公开(公告)号：US06157967A

公开(公告)日：2000-12-05

申请号：US1100

申请日：1997-12-30

申请人： Robert W. Horst ,  William Edward Baker ,  Linda Ellen Zalzala ,  William Patterson Bunton ,  Richard W. Cutts, Jr. ,  David J. Garcia ,  John C. Krause ,  Stephen G. Low ,  David Paul Sonnier ,  William Joel Watson ,  Patracia L. Whiteside

发明人： Robert W. Horst ,  William Edward Baker ,  Linda Ellen Zalzala ,  William Patterson Bunton ,  Richard W. Cutts, Jr. ,  David J. Garcia ,  John C. Krause ,  Stephen G. Low ,  David Paul Sonnier ,  William Joel Watson ,  Patracia L. Whiteside

IPC分类号： G06F11/00 ,  G06F15/173 ,  H04L1/16

CPC分类号： G06F15/17381

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US5751932A

公开(公告)日：1998-05-12

申请号：US485217

申请日：1995-06-07

申请人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

发明人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 CPU被构造为以两种模式之一操作：两个CPU彼此独立地操作的单工模式，以及CPU以锁步同步操作的双工模式，以基本上执行相同指令流的每条指令 同一时间。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US5790776A

公开(公告)日：1998-08-04

申请号：US485053

申请日：1995-06-07

申请人： David Paul Sonnier ,  William Edward Baker ,  William Patterson Bunton ,  John C. Krause ,  Kenneth H. Porter ,  William Joel Watson ,  Linda Ellen Zalzala

发明人： David Paul Sonnier ,  William Edward Baker ,  William Patterson Bunton ,  John C. Krause ,  Kenneth H. Porter ,  William Joel Watson ,  Linda Ellen Zalzala

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US5964835A

公开(公告)日：1999-10-12

申请号：US482618

申请日：1995-06-07

申请人： Daniel L. Fowler ,  William Edward Baker ,  William Patterson Bunton ,  Gary F. Campbell ,  Richard W. Cutts, Jr. ,  David J. Garcia ,  Paul N. Hintikka ,  Robert W. Horst ,  Geoffrey I. Iswandhi ,  David P. Sonnier ,  William Joel Watson ,  Frank A. Williams

发明人： Daniel L. Fowler ,  William Edward Baker ,  William Patterson Bunton ,  Gary F. Campbell ,  Richard W. Cutts, Jr. ,  David J. Garcia ,  Paul N. Hintikka ,  Robert W. Horst ,  Geoffrey I. Iswandhi ,  David P. Sonnier ,  William Joel Watson ,  Frank A. Williams

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括多个中央处理单元（CPU）和至少一个输入/输出（I / O）设备，其通过路由设备互连，用于在其间传送分组消息。 消息包含标识消息的源和目的地的地址信息，并且还可以包含写入或读取CPU的存储的请求。 通过使用由每个CPU维护的多个条目中包含的访问验证信息的访问验证方法来提供对错误读取或写入的保护。 每个条目通过确定系统的哪些元素已读取和/或将wccss写入该CPU的内存来进行验证，而不会拒绝该内存访问。

公开(公告)号：US5675579A

公开(公告)日：1997-10-07

申请号：US474770

申请日：1995-06-07

申请人： William Joel Watson ,  William Edward Baker ,  William F. Bruckert ,  William Patterson Bunton ,  David J. Garcia ,  Robert W. Horst ,  Geoffrey I. Iswandhi ,  David Joseph Kinkade ,  David Paul Sonnier

发明人： William Joel Watson ,  William Edward Baker ,  William F. Bruckert ,  William Patterson Bunton ,  David J. Garcia ,  Robert W. Horst ,  Geoffrey I. Iswandhi ,  David Joseph Kinkade ,  David Paul Sonnier

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  H04L1/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.

摘要翻译： 处理系统包括多个以通信方式互连的系统元件，其被构造为以消息分组的形式发送和接收数据。 发送到具有期望响应的目的地的消息分组被定时，并且如果在分配的时间内没有收到响应，则将屏障事务消息分组发送到目的地。 只有在响应或丢弃所有先前接收到的需要目的地响应的消息分组之后，目的地才需要向屏障事务分组提供屏障事务响应。 当屏障事务消息分组的源接收到屏障事务响应时，可以确保目的地的通信路径是顺序的，并且不会有即将到来的（迟）响应。

公开(公告)号：US5751955A

公开(公告)日：1998-05-12

申请号：US473541

申请日：1995-06-07

申请人： David Paul Sonnier ,  William Edward Baker ,  William Patterson Bunton ,  Daniel L. Fowler ,  Curtis Willard Jones, Jr. ,  John C. Krause ,  Michael P. Simpson ,  William Joel Watson

发明人： David Paul Sonnier ,  William Edward Baker ,  William Patterson Bunton ,  Daniel L. Fowler ,  Curtis Willard Jones, Jr. ,  John C. Krause ,  Michael P. Simpson ,  William Joel Watson

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US5675807A

公开(公告)日：1997-10-07

申请号：US481749

申请日：1995-06-07

申请人： Geoffrey I. Iswandhi ,  William Edward Baker ,  William Patterson Bunton ,  John Deane Coddington ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Susan Stone Meredith ,  Stephen H. Miller ,  David Paul Sonnier ,  William Joel Watson ,  Frank A. Williams

发明人： Geoffrey I. Iswandhi ,  William Edward Baker ,  William Patterson Bunton ,  John Deane Coddington ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Susan Stone Meredith ,  Stephen H. Miller ,  David Paul Sonnier ,  William Joel Watson ,  Frank A. Williams

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或与系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息分组，并存储在存储器中的中断队列中。 中断数据的存储将启动内部中断以通知接收CPU。 然后，接收CPU可以访问中断队列，检查中断数据，并确定要采取的操作。

公开(公告)号：US11718438B1

公开(公告)日：2023-08-08

申请号：US17386623

申请日：2021-07-28

申请人： William Edward Baker

发明人： William Edward Baker

IPC分类号： B65D1/02 ,  B67D3/00

CPC分类号： B65D1/0246 ,  B67D3/0051

摘要： A fuel additive bottle has a neck and thread pattern that allows insertion into a capless diesel fuel system so the bottle's contents can be poured by gravity into a fuel tank. The neck of the bottle is elongated and has a diameter of approximately 0.932 inches, and the novel thread pattern includes thread interruptions that form two or four threadless paths. In use, the spring loaded tabs of a capless fuel system are depressed by the threadless path portion of bottle, thereby triggering the self-sealing mechanism to open, so the fluid receiving aperture is exposed. The use of the threadless paths facilitates the safe and easy entry and removal of the bottle from the capless fuel system.

公开(公告)号：US10442563B2

公开(公告)日：2019-10-15

申请号：US15867931

申请日：2018-01-11

申请人： William Edward Baker

发明人： William Edward Baker

IPC分类号： B65D1/02 ,  B67D3/00

摘要： A fuel additive bottle has a neck and thread pattern that allows insertion into a capless fuel system so the bottle's contents can be poured by gravity into a fuel tank. The neck of the bottle is elongated and has a diameter of approximately 0.854″, and the novel thread pattern includes thread interruptions that form at least one threadless path. In use, the spring loaded tabs of a capless fuel system are depressed by the threadless path portion of bottle, thereby triggering the self-sealing mechanism to open, so the fluid receiving aperture is exposed. The use of the threadless paths facilitates the safe and easy entry and removal of the bottle from the capless fuel system.

公开(公告)号：US09889961B2

公开(公告)日：2018-02-13

申请号：US13937568

申请日：2013-07-09

申请人： William Edward Baker

发明人： William Edward Baker

IPC分类号： B65D1/02 ,  B67D3/00

CPC分类号： B65D1/0246 ,  B67D3/0051

摘要： A fuel additive bottle has a neck and thread pattern that allows insertion into a capless fuel system so the bottle's contents can be poured by gravity into a fuel tank. The neck of the bottle is elongated and has a diameter of approximately 0.854″, and the novel thread pattern includes thread interruptions that form at least one threadless path. In use, the spring loaded tabs of a capless fuel system are depressed by the threadless path portion of bottle, thereby triggering the self-sealing mechanism to open, so the fluid receiving aperture is exposed. The use of the threadless paths facilitates the safe and easy entry and removal of the bottle from the capless fuel system.