Automatic layout for cascode voltage switch logic
    3.
    发明授权
    Automatic layout for cascode voltage switch logic 失效
    级联电压开关逻辑的自动布局

    公开(公告)号:US4627152A

    公开(公告)日:1986-12-09

    申请号:US737614

    申请日:1985-05-24

    CPC分类号: G06F17/5068

    摘要: A method for automatically laying out a circuit starting from a logic gate diagram, especially for a CMOS technology. The logic is divided into blocks having a maximum number of serially connected transistors. Then the transistors are ordered to maximize the number of contiguously connected transistors. The ordered transistors then have their remaining connections determined according to the type of logic gate they represent.

    摘要翻译: 一种从逻辑门图开始自动布局电路的方法,特别是对于CMOS技术。 该逻辑被分成具有串联连接的最大数量的晶体管的块。 然后对晶体管进行排序以使连续连接的晶体管的数量最大化。 然后,有序晶体管的剩余连接根据它们所代表的逻辑门的类型确定。