公开(公告)号：US5604879A

公开(公告)日：1997-02-18

申请号：US653677

申请日：1996-05-23

申请人： Brad Beavers ,  Chua-Eoan Lew ,  Pei-Chun Liu ,  Chih-Jui Peng

发明人： Brad Beavers ,  Chua-Eoan Lew ,  Pei-Chun Liu ,  Chih-Jui Peng

IPC分类号： G06F12/10

CPC分类号： G06F12/1036

摘要： A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.

摘要翻译： CAM / SRAM结构（44）执行与分段/寻呼寻址方案兼容但仅需要单个查找步骤的地址转换。 有效到实地址转换器（ERAT）中的每个条目具有分别独立地将输入段标识符和输入页标识符与存储的段标识符和存储的页标识符进行独立比较的两个CAM字段（ESID，EPI）。 如果两个比较是等效的，ERAT输出与存储的段存储的页对相关联的存储的实际地址字段（DATA）。 在无效操作期间，ERAT可以通过分别要求分段或页面CAM字段匹配来使分段或页面粒度的存储转换无效。

公开(公告)号：US06463514B1

公开(公告)日：2002-10-08

申请号：US09025605

申请日：1998-02-18

申请人： David Scott Ray ,  Shih-Hsiung Stephen Tung ,  Pei Chun Liu

发明人： David Scott Ray ,  Shih-Hsiung Stephen Tung ,  Pei Chun Liu

IPC分类号： G06F1200

CPC分类号： G06F12/0851 ,  G06F12/0857

摘要： A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.

摘要翻译： 响应于检测到第一高速缓存地址和第二高速缓存地址之间的冲突而通过停止第一高速缓存访​​问电路来在高速缓存访​​问电路之间进行仲裁（即，加载/存储单元）的方法。 响应于第一和第二高速缓存地址中的每一个中的一个或多个子阵列选择位的比较来执行停滞，并且还优选地包括用于第一和第二高速缓存存取电路的公共竞争逻辑单元。 第一高速缓存地址被保留在第一高速缓存访​​问电路内，使得第一高速缓存访​​问电路不需要重新生成第一高速缓存地址。 如果通过多个加载操作访问相同的字（或双字），则该条件不被认为是争用，并且两个操作都被允许继续进行，即使它们在交错高速缓存的相同子阵列中。

公开(公告)号：US6064245A

公开(公告)日：2000-05-16

申请号：US26087

申请日：1998-02-19

申请人： Rajinder Paul Singh ,  Pei-Chun Liu ,  Song Kim

发明人： Rajinder Paul Singh ,  Pei-Chun Liu ,  Song Kim

IPC分类号： H03K3/356 ,  H03K3/027

CPC分类号： H03K3/356139

摘要： The present invention is directed to an apparatus for precharging complementary data circuits. The apparatus comprises two hold circuits, one for storing the data and the other for storing its complement. A signal for initiates precharging the hold circuits to the same signal level, where the signal for initiating the precharging of the hold circuits is dependent on the hold circuits' outputs.

摘要翻译： 本发明涉及一种用于对互补数据电路进行预充电的装置。 该装置包括两个保持电路，一个用于存储数据，另一个用于存储其补码。 用于启动将保持电路预充电到相同信号电平的信号，其中用于启动保持电路的预充电的信号取决于保持电路的输出。