公开(公告)号：US07003648B2

公开(公告)日：2006-02-21

申请号：US10109255

申请日：2002-03-28

Applicant: George Z. Chrysos ,  Chuan-Hua Chang ,  Joel S. Emer ,  John H. Mylius ,  Peter Soderquist

Inventor： George Z. Chrysos ,  Chuan-Hua Chang ,  Joel S. Emer ,  John H. Mylius ,  Peter Soderquist

IPC: G06F15/82 ,  G06F15/163

CPC classification number: G06F9/3855 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857

Abstract: A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.