公开(公告)号：US09600289B2

公开(公告)日：2017-03-21

申请号：US13483268

申请日：2012-05-30

申请人： Stephan G. Meier ,  John H. Mylius ,  Gerard R. Williams, III ,  Suparn Vats

发明人： Stephan G. Meier ,  John H. Mylius ,  Gerard R. Williams, III ,  Suparn Vats

IPC分类号： G06F12/1018 ,  G06F12/0864 ,  G06F17/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F12/0864 ,  G06F12/1018 ,  G06F17/30949

摘要： Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value.

公开(公告)号：US20130290681A1

公开(公告)日：2013-10-31

申请号：US13460178

申请日：2012-04-30

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

IPC分类号： G06F9/30

CPC分类号： G06F9/30141 ,  G06F1/3234 ,  G06F9/30112 ,  G06F9/384

摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。

公开(公告)号：US20130275720A1

公开(公告)日：2013-10-17

申请号：US13447651

申请日：2012-04-16

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/30032 ,  G06F9/384

摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

公开(公告)号：US20080250275A1

公开(公告)日：2008-10-09

申请号：US11697428

申请日：2007-04-06

申请人： Kevin R. Walker ,  John H. Mylius

发明人： Kevin R. Walker ,  John H. Mylius

IPC分类号： G06F11/34

CPC分类号： G06F11/3636 ,  G06F11/3476

摘要： In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

摘要翻译： 在一个实施例中，集成电路包括被配置为输出程序计数器（PC）跟踪记录的第一处理器，其中PC跟踪记录提供指示由第一处理器退休的指令的PC的数据。 集成电路还包括跟踪记录的第二源，以及耦合以从第一处理器接收PC跟踪记录和来自第二源的跟踪记录的跟踪单元。 跟踪单元包括跟踪单元，跟踪单元被配置为存储来自第二个源的PC跟踪记录和跟踪记录。 跟踪单元被配置为根据记录的接收顺序将跟踪记录和跟踪记录中的跟踪记录交错在跟踪存储器中。

公开(公告)号：US20130339671A1

公开(公告)日：2013-12-19

申请号：US13517865

申请日：2012-06-14

申请人： Gerard R. Williams, III ,  John H. Mylius ,  Conrade Blasco-Allue

发明人： Gerard R. Williams, III ,  John H. Mylius ,  Conrade Blasco-Allue

IPC分类号： G06F9/30 ,  G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/30181 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/384

摘要： A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction.

摘要翻译： 一种用于减少加载操作延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的加载指令是否符合转换为零周期加载操作的资格。 如果是这样，则控制逻辑将与旧的从属存储指令的源操作数相关联的物理寄存器标识分配给加载指令的目的地操作数。 此外，寄存器重命名单元标记加载指令以防止其从存储器读取与存储指令的源操作数相关联的数据。 由于重复重命名，该数据可能会从物理寄存器文件转发到更年轻且取决于加载指令的指令。

公开(公告)号：US20130191677A1

公开(公告)日：2013-07-25

申请号：US13355023

申请日：2012-01-20

申请人： Conrad H. Ziesler ,  John H. Mylius ,  Jason M. Kassoff

发明人： Conrad H. Ziesler ,  John H. Mylius ,  Jason M. Kassoff

IPC分类号： G06F1/10 ,  H03K3/017

CPC分类号： G06F1/10 ,  G06F1/3237 ,  H03K19/0016 ,  Y02D10/128

摘要： A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.

摘要翻译： 公开了一种用于在空闲时间期间抖动时钟信号的系统和方法。 集成电路（IC）包括多个功能单元和时钟树。 时钟树包括根电平时钟门控电路，多个区域时钟门控电路和多个叶电平时钟门控电路。 根电平时钟门控电路被耦合以将操作时钟信号分配给区域时钟门控电路，而区域时钟门控电路各自被配置为将操作时钟信号分配给对应的叶级别门控时钟信号 电路。 IC还可以包括控制单元，其被配置为监视来自每个功能单元的活动水平和指示。 如果IC空闲，则控制单元可以使根时钟选通电路对时钟信号进行抖动，其中抖动包括降低工作时钟信号的占空比和有效频率。

公开(公告)号：US20120290818A1

公开(公告)日：2012-11-15

申请号：US13557725

申请日：2012-07-25

申请人： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

发明人： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

IPC分类号： G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

摘要翻译： 在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。 其他依赖关系在第二个依赖关系数组中被跟踪。 第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。 第二个数组可能比第一个依赖数组慢得多。

公开(公告)号：US07984338B2

公开(公告)日：2011-07-19

申请号：US12774346

申请日：2010-05-05

申请人： Kevin R. Walker ,  John H. Mylius

发明人： Kevin R. Walker ,  John H. Mylius

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3476

摘要： In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

摘要翻译： 在一个实施例中，集成电路包括被配置为输出程序计数器（PC）跟踪记录的第一处理器，其中PC跟踪记录提供指示由第一处理器退休的指令的PC的数据。 集成电路还包括跟踪记录的第二源，以及耦合以从第一处理器接收PC跟踪记录和来自第二源的跟踪记录的跟踪单元。 跟踪单元包括跟踪单元，跟踪单元被配置为存储来自第二个源的PC跟踪记录和跟踪记录。 跟踪单元被配置为根据记录的接收顺序将跟踪记录和跟踪记录中的跟踪记录交错在跟踪存储器中。

公开(公告)号：US09996348B2

公开(公告)日：2018-06-12

申请号：US13517865

申请日：2012-06-14

申请人： Gerard R. Williams, III ,  John H. Mylius ,  Conrade Blasco-Allue

发明人： Gerard R. Williams, III ,  John H. Mylius ,  Conrade Blasco-Allue

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30181 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/384

摘要： A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction.

公开(公告)号：US20140013085A1

公开(公告)日：2014-01-09

申请号：US13541351

申请日：2012-07-03

申请人： Suparn Vats ,  John H. Mylius ,  Abhijit Radhakrishnan

发明人： Suparn Vats ,  John H. Mylius ,  Abhijit Radhakrishnan

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/384

摘要： A system and method for reducing latency and power of register renaming. A free list in processor includes multiple banks for indicating availability of register identifiers used for register renaming. A register rename unit receives one or more destination architectural registers to rename with physical register identifiers. Responsive to determining the multiple banks within the free list are unbalanced with available physical register identifiers, one or more returning physical register identifiers are assigned to the destination architectural registers before assigning any physical register identifiers from any bank of the multiple banks with a lowest number of available physical register identifiers. A returning physical register identifier is a physical register identifier that is available again for assignment to a destination architectural register but not yet indicated in the free list as available. Each of the banks includes a single bit width decoded vector for indicating availability of given physical register identifiers.

摘要翻译： 一种用于减少寄存器重命名的等待时间和功率的系统和方法。 处理器中的一个空白列表包括用于指示用于寄存器重命名的寄存器标识符的可用性的多个存储单元。 寄存器重命名单元接收一个或多个目的地体系结构寄存器以用物理寄存器标识符重命名。 响应于确定空闲列表中的多个存储体与可用的物理寄存器标识符不平衡，一个或多个返回物理寄存器标识符被分配给目的地架构寄存器，然后从具有最低数量 可用的物理寄存器标识符。 返回的物理寄存器标识符是物理寄存器标识符，可以再次用于分配到目的地架构寄存器，但尚未在可用的空闲列表中指示。 每个存储体包括用于指示给定物理寄存器标识符的可用性的单个位宽解码向量。