公开(公告)号：US5260936A

公开(公告)日：1993-11-09

申请号：US904084

申请日：1992-06-25

申请人： Gerard Bardet ,  Jean-Francois Le Pennec ,  Patrick Michel ,  Philippe Therias

发明人： Gerard Bardet ,  Jean-Francois Le Pennec ,  Patrick Michel ,  Philippe Therias

IPC分类号： H04L29/02 ,  H04L1/00 ,  H04L12/56 ,  H04L13/08 ,  H04L29/08 ,  H03M13/00

CPC分类号： H04L12/56 ,  H04L1/0078

摘要： A store and forward apparatus includes a deserializer for deserializing received frames of data into a sequence of n-bit words. Each frame includes a header, a data field and a frame checking sequence (FCS) generated by a first telecommunication node. The apparatus includes a storage for storing the deserialized n-bit words, and a processor for addressing the storage and for generating n-bit words corresponding to a new header of the received frame. The apparatus also includes a serializer receiving the n-bit words from the storage for generating a new frame having a new header field and a new FCS to be transmitted to a second telecommunication node. The apparatus further includes a receiver for receiving a frame and computes a first partial FCS covering the frame's data field only and a storage for storing the first partial FCS. During forwarding, n-bit words to be transmitted are simultaneously received by the serializer and by an apparatus for computing a second partial FCS covering the data field only. At the end of the serialization process, the two partial FCS results are compared to detect an error occurring during the computing of the new header of the frame. The result of the comparison is used as a control signal for altering the value of the FCS computed by serializer prior to transmission.

公开(公告)号：US5043989A

公开(公告)日：1991-08-27

申请号：US401892

申请日：1989-09-01

申请人： Philippe Dalmas ,  Daniel Esteban ,  Jean-Francois Le Pennec ,  Patrick Michel ,  Philippe Therias

发明人： Philippe Dalmas ,  Daniel Esteban ,  Jean-Francois Le Pennec ,  Patrick Michel ,  Philippe Therias

IPC分类号： H04L29/04 ,  H04L1/00 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  H04L1/0045 ,  H04L1/0061 ,  H04L69/324

摘要： A terminal adapter for a telecommunication network having a receiver for multiple HDLC communication channels. The receiver includes a BCC calculator for computing and checking the validity of a received HDLC CNM frame. The terminal adapter further includes a device for detecting the reception of a specific CNM header included in a CNM frame on any of the HDLC communication channels and responsive to the detection for setting the BCC calculator to a predefined state. The latter state corresponds to the state of the BCC calculator after a computation of BCC for the specific CNM header. Therefore the BCC calculator can proceed with computation of said BCC for the CNM frame.

公开(公告)号：US5214771A

公开(公告)日：1993-05-25

申请号：US401895

申请日：1989-09-01

申请人： Jean-Louis Clara ,  Philippe Jachimczyk ,  Jean-Freancois Le Pennec ,  Louis Massiera ,  Philippe Therias

发明人： Jean-Louis Clara ,  Philippe Jachimczyk ,  Jean-Freancois Le Pennec ,  Louis Massiera ,  Philippe Therias

IPC分类号： G06F13/14 ,  G06F12/06

CPC分类号： G06F12/0684

摘要： Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor. The different memory and peripheral elements include first memory elements and first peripheral elements located in a first adapter pluggable into a base machine and second memory elements and second peripheral elements located into a second adapter pluggable into the base machine. The processor further addresses third memory elements and third peripheral elements located in the base machine. The first and second memory elements include code which has a determined type and a determined level of release. The invention is characterized in the fact that it further includes a mechanism for reading the type and the level of the release of said code included in one of said first and second adapters and mechanisms responsive to said reading and operating when said codes of both of said first and second adapters are of the same type for selecting that code of said first or second memory which has the code of higher level of release when said processor desires to access the code of a given type in one of said adapters.