公开(公告)号：US5214771A

公开(公告)日：1993-05-25

申请号：US401895

申请日：1989-09-01

申请人： Jean-Louis Clara ,  Philippe Jachimczyk ,  Jean-Freancois Le Pennec ,  Louis Massiera ,  Philippe Therias

发明人： Jean-Louis Clara ,  Philippe Jachimczyk ,  Jean-Freancois Le Pennec ,  Louis Massiera ,  Philippe Therias

IPC分类号： G06F13/14 ,  G06F12/06

CPC分类号： G06F12/0684

摘要： Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor. The different memory and peripheral elements include first memory elements and first peripheral elements located in a first adapter pluggable into a base machine and second memory elements and second peripheral elements located into a second adapter pluggable into the base machine. The processor further addresses third memory elements and third peripheral elements located in the base machine. The first and second memory elements include code which has a determined type and a determined level of release. The invention is characterized in the fact that it further includes a mechanism for reading the type and the level of the release of said code included in one of said first and second adapters and mechanisms responsive to said reading and operating when said codes of both of said first and second adapters are of the same type for selecting that code of said first or second memory which has the code of higher level of release when said processor desires to access the code of a given type in one of said adapters.