公开(公告)号：US5926487A

公开(公告)日：1999-07-20

申请号：US583297

申请日：1996-01-05

申请人： Terry Ivan Chappell ,  Michael Kevin Ciraula ,  Max Eduardo De Ycaza ,  Sang Hoo Dhong ,  Rudolf Adriaan Haring ,  Talal Kamel Jaber ,  Mark Samson Milshtein ,  Pho Hoang Nguyen ,  Edward Seewann

发明人： Terry Ivan Chappell ,  Michael Kevin Ciraula ,  Max Eduardo De Ycaza ,  Sang Hoo Dhong ,  Rudolf Adriaan Haring ,  Talal Kamel Jaber ,  Mark Samson Milshtein ,  Pho Hoang Nguyen ,  Edward Seewann

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/31853

摘要： A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.

摘要翻译： 描述了可以用作使用脉冲逻辑方法设计的逻辑芯片中的流水线寄存器的高性能寄存器。 寄存器具有最小的建立时间，脉冲捕获和脉冲启动。 寄存器电路符合并实施脉冲逻辑的电路级测试方法，该方法具有禁止脉冲复位的能力，强制复位和以伪静态模式操作电路。 寄存器还符合级别敏感扫描设计（LSSD）方法。 还描述了一种符合脉冲逻辑设计方法的状态保持静态主从寄存器，该寄存器具有自动功率降低特征和简化的模块寄存器位设计，其可以容易地适用于静态多米诺或脉冲逻辑。 该寄存器也符合LSSD标准。 还描述了允许静态传输门输入寄存器符合静态评估测试模式的手段和方法。 自动降功能可扩展到下游逻辑。