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公开(公告)号：US08365056B2
公开(公告)日：2013-01-29
申请号：US12796272
申请日：2010-06-08
IPC分类号： H03M13/03
CPC分类号： H03M13/4161 , H03M13/41 , H03M13/6516 , H03M13/6569
摘要： A receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the signal received including a series of symbols, is provided. The receiver comprises a programmable logic circuit that includes a source memory A and a destination memory B each comprising N rows and M+L columns respectively allocated to M fixed fields for describing the trellis, and to L variable fields, and an operator able to calculate the variable fields of a memory as a function of the fixed fields of the said memory, of the symbols received and of the variable fields of the other memory and able to reverse the role of the source memory and destination memory.
摘要翻译： 提供了配备有N状态加权决策网格维特比解码器的数字信号的接收机，所述信号包括一系列符号。 接收机包括可编程逻辑电路，其包括源存储器A和目的地存储器B，每个存储器包括分别分配给用于描述网格的M个固定字段的N行和M + L列，以及L个可变字段，以及能够计算 作为所述存储器的固定字段，接收到的符号和另一存储器的可变字段的函数的存储器的可变字段，并且能够反转源存储器和目的地存储器的作用。
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公开(公告)号：US20100313103A1
公开(公告)日：2010-12-09
申请号：US12796272
申请日：2010-06-08
CPC分类号： H03M13/4161 , H03M13/41 , H03M13/6516 , H03M13/6569
摘要： A receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the signal received including a series of symbols, is provided. The receiver comprises a programmable logic circuit that includes a source memory A and a destination memory B each comprising N rows and M+L columns respectively allocated to M fixed fields for describing the trellis, and to L variable fields, and an operator able to calculate the variable fields of a memory as a function of the fixed fields of the said memory, of the symbols received and of the variable fields of the other memory and able to reverse the role of the source memory and destination memory.
摘要翻译： 提供了配备有N状态加权决策网格维特比解码器的数字信号的接收机，所述信号包括一系列符号。 接收机包括可编程逻辑电路，其包括源存储器A和目的地存储器B，每个存储器包括分别分配给用于描述网格的M个固定字段的N行和M + L列，以及L个可变字段，以及能够计算 作为所述存储器的固定字段，接收到的符号和另一存储器的可变字段的函数的存储器的可变字段，并且能够反转源存储器和目的地存储器的作用。
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公开(公告)号：US20110095943A1
公开(公告)日：2011-04-28
申请号：US12757300
申请日：2010-04-09
IPC分类号： G01S19/32
CPC分类号： H04B1/0071 , G01S19/32 , G01S19/33 , G01S19/36
摘要： A multifrequency receiver comprises a first receiving subsystem comprising: means for receiving at least a first and a second distinct frequency at least one of which comprises a signal containing information relating to the position of a satellite, the said receiving means comprising: a first amplification stage delivering a first filtered signal based on the signal received by the receiver; a second stage for processing each of the received frequencies; a third stage comprising a mixer and at least one local oscillator; and a fourth amplification and filtering stage making it possible to amplify the filtered signal at the output of the mixer. The second stage comprises: a first switch; means for amplifying the signals of the two channels; and a second switch making it possible to deliver the signal to the third stage.
摘要翻译： 多频接收机包括：第一接收子系统，包括：用于接收至少一个第一和第二不同频率的装置，其中的至少一个包括包含与卫星位置有关的信息的信号，所述接收装置包括：第一放大级 基于由接收机接收的信号传送第一滤波信号; 用于处理每个所接收的频率的第二级; 第三级，包括混频器和至少一个本地振荡器; 以及第四放大和滤波级，使得可以在混频器的输出处放大经滤波的信号。 第二级包括：第一开关; 用于放大两个信道的信号的装置; 以及第二开关，使得可以将信号传递到第三级。
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