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    Decoding path selection device and method
    1.
    发明授权
    Decoding path selection device and method 有权

    公开(公告)号：US09787331B1

    公开(公告)日：2017-10-10

    申请号：US15224939

    申请日：2016-08-01

    申请人： YUAN ZE UNIVERSITY

    发明人： Cheng-Hung Lin ,  Tsung-Ju Hsieh

    IPC分类号： H03M13/03 ,  H03M13/39 ,  H03M13/23 ,  H03M13/25 ,  H03M13/41

    CPC分类号： H03M13/4161 ,  H03M13/3905 ,  H03M13/395

    摘要： The present invention discloses a decoding path selection device for decoding codewords generated by convolutional codes or turbo codes encoders in error correction codes, the decoding path selection device comprising: a branch metrics calculation unit for receiving incoming signals and calculating branch metrics values; a programmable generalized trellis router for generating a decoding path control signal according to the turbo code or convolutional code specification employed by one of communications standards; a multiplexer for receiving the branch metrics values from the branch metrics calculation unit and the decoding path control signal from the programmable generalized trellis router and selecting a corresponding branch metrics value; a recursive calculation unit, connected after the multiplexer and for receiving the corresponding branch metrics value from the multiplexer; and an a-posteriori probability calculation unit, connected after the recursive calculation unit and for calculating a final decoding result.

    METHOD AND APPARATUS FOR REDUCING FALSE DECODING
    2.
    发明申请
    METHOD AND APPARATUS FOR REDUCING FALSE DECODING 审中-公开
    减少伪装置的方法和装置

    公开(公告)号：US20170033807A1

    公开(公告)日：2017-02-02

    申请号：US15211486

    申请日：2016-07-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Daeson KIM ,  Mingoo KIM ,  Chaehag YI

    IPC分类号： H03M13/41 ,  H04L12/26

    CPC分类号： H03M13/4115 ,  H03M13/4161 ,  H03M13/4169

    摘要： Methods and apparatuses are provided for operating a list Viterbi decoder. A path metric difference (PMD) threshold is set based on an input signal level and a PMD limit value. Decoding is performed by using the PMD threshold. Performing the decoding includes determining a PMD of a best path, comparing the determined PMD and the PMD threshold, and declaring a decoding failure and ending performing of the decoding, if the PMD is greater than or equal to the PMD threshold.

    摘要翻译： 提供了用于操作列表维特比解码器的方法和装置。 基于输入信号电平和PMD极限值设置路径度量差（PMD）阈值。 通过使用PMD阈值进行解码。 如果PMD大于或等于PMD阈值，则执行解码包括确定最佳路径的PMD，比较确定的PMD和PMD阈值，并声明解码失败并结束执行解码。

    Bitwise reliability indicators from survivor bits in Viterbi decoders
    3.
    发明授权
    Bitwise reliability indicators from survivor bits in Viterbi decoders 有权
    维特比解码器中存活位的逐位可靠性指标

    公开(公告)号：US08433975B2

    公开(公告)日：2013-04-30

    申请号：US12856143

    申请日：2010-08-13

    申请人： Andries Pieter Hekstra ,  Nur Engin

    发明人： Andries Pieter Hekstra ,  Nur Engin

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0054 ,  H03M13/09 ,  H03M13/2936 ,  H03M13/373 ,  H03M13/4138 ,  H03M13/4161 ,  H04L1/0059 ,  H04L1/0065

    摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

    摘要翻译： 各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。 维特比解码器可以使用寄存器交换方法来产生多个幸存代码。 在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。 这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。 可以将高阶位与低位的差的绝对值与定义的阈值进行比较。 当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。 在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

    Systems and Methods for Sequence Detection in Data Processing
    5.
    发明申请
    Systems and Methods for Sequence Detection in Data Processing 有权
    数据处理中序列检测的系统和方法

    公开(公告)号：US20120036173A1

    公开(公告)日：2012-02-09

    申请号：US12851475

    申请日：2010-08-05

    申请人： Viswanath Annampedu

    发明人： Viswanath Annampedu

    IPC分类号： G06F17/15

    CPC分类号： G11B20/10009 ,  G11B20/10055 ,  G11B20/10277 ,  G11B20/10296 ,  H03M13/4161 ,  H04L25/03184

    摘要： Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value.

    摘要翻译： 本发明的各种实施例提供了用于序列检测的系统和方法。 作为示例，公开了一种用于数据检测的方法，包括：在检测器电路处接收一系列数据样本; 将所述一系列数据样本的一部分乘以对应于第一二进制转换的第一相关器值以产生第一值; 将所述一系列数据样本的所述部分乘以对应于第二二进制转换的第二相关器值以产生第二值; 将所述第一值添加到先前状态值以产生第一中间值; 将所述第二值添加到所述先前状态值以产生第二临时值; 并且选择第一临时值和第二临时值中较大的一个以产生存活的临时值。

    LDPC (Low Density Parity Check) coded modulation symbol decoding
    7.
    发明申请
    LDPC (Low Density Parity Check) coded modulation symbol decoding 有权
    LDPC（低密度奇偶校验）编码调制符号解码

    公开(公告)号：US20110072336A1

    公开(公告)日：2011-03-24

    申请号：US12957238

    申请日：2010-11-30

    申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

    发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

    IPC分类号： G06F11/00

    CPC分类号： H04L27/2602 ,  G11B20/1833 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/25 ,  H03M13/255 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/4161 ,  H03M13/45 ,  H03M13/6516 ,  H03M13/6583 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/1671 ,  H04L27/18

    摘要： LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

    摘要翻译： LDPC（低密度奇偶校验）编码调制符号解码。 通过适当地修改LDPC三部分图来消除比特节点从而生成LDPC二分图（使得符号节点被适当地映射到校验节点从而消除比特节点）来支持符号解码。 将符号节点通信地耦合到校验节点的边缘被适当地标记以支持LDPC编码调制信号的符号解码。 迭代解码处理可以包括更新校验节点以及估计符号序列和更新符号节点。 在一些实施例中，可以执行替代的混合解码方法，使得执行位电平和符号电平解码的组合。 该LDPC码解码仅执行比特解码。 此外，它提供可比较或更好的比特解码性能，涉及相关度量的迭代更新。

    Bit detection for multitrack digital data storage
    8.
    发明授权
    Bit detection for multitrack digital data storage 失效
    多轨数字数据存储的位检测

    公开(公告)号：US07900124B2

    公开(公告)日：2011-03-01

    申请号：US11718407

    申请日：2005-11-07

    申请人： Thomas Conway ,  Richard Conway

    发明人： Thomas Conway ,  Richard Conway

    IPC分类号： H03M13/03 ,  G11B20/10

    CPC分类号： G11B20/10287 ,  G11B20/10009 ,  G11B20/10296 ,  G11B20/22 ,  H03M13/41 ,  H03M13/4161

    摘要： The use of a multi-track format in both optical and magnetic data storage applications provides for a number of improvements to system performance including data density and data transfer rates. However, the full advantage in data density can only be achieved through the use of joint equalization and joint detection. The complexity of implementation of these functions arc addressed with a transform domain equalization architecture and a reduced complexity detection method based on a breadth first search of a time-varying trellis. The trellis results from a one dimensional representation of a two dimensional target response, obtained by arranging samples from adjacent tracks in a sequence that respects the original proximity of the samples.

    摘要翻译： 在光学和磁性数据存储应用中使用多轨道格式提供了对数据密度和数据传输速率的系统性能的许多改进。 然而，数据密度的全部优点只能通过使用联合均衡和联合检测来实现。 这些功能的实现的复杂性通过变换域均衡架构和基于时变网格的广度优先搜索的降低的复杂度检测方法来解决。 网格由二维目标响应的一维表示产生，该二维目标响应通过以相对于样本的原始邻近度的顺序排列来自相邻轨道的样本而获得。

    ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING
    9.
    发明申请
    ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING 有权
    基于TRLLIS的检测和/或解码的错误模式生成

    公开(公告)号：US20100269026A1

    公开(公告)日：2010-10-21

    申请号：US12824517

    申请日：2010-06-28

    申请人： Shaohua Yang ,  Seo-How Low ,  Zining Wu ,  Gregory Burd

    发明人： Shaohua Yang ,  Seo-How Low ,  Zining Wu ,  Gregory Burd

    IPC分类号： H03M13/41 ,  H03M13/03 ,  G06F11/00

    CPC分类号： H03M13/4192 ,  H03M13/098 ,  H03M13/3994 ,  H03M13/4138 ,  H03M13/4161 ,  H03M13/4169

    摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.

    摘要翻译： 所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。 在本发明的一个方面，所公开的技术检测先前基于网格编码的信息，并且基于网格对检测到的信息进行解码以提供解码信息。 解码的信息对应于通过在获胜状态结束的网格的获胜路径。 所公开的技术可以识别通过网格的一个或多个备选路径，其也以胜利状态结束，并且可以为每个备选路径生成潜在的错误模式。

    Error pattern generation for trellis-based detection and/or decoding
    10.
    发明授权
    Error pattern generation for trellis-based detection and/or decoding 有权
    基于网格的检测和/或解码的错误模式生成

    公开(公告)号：US07765458B1

    公开(公告)日：2010-07-27

    申请号：US11518020

    申请日：2006-09-08

    申请人： Shaohua Yang ,  Seo-How Low ,  Zining Wu ,  Gregory Burd

    发明人： Shaohua Yang ,  Seo-How Low ,  Zining Wu ,  Gregory Burd

    IPC分类号： H03M13/41

    CPC分类号： H03M13/4192 ,  H03M13/098 ,  H03M13/3994 ,  H03M13/4138 ,  H03M13/4161 ,  H03M13/4169

    摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.

    摘要翻译： 所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。 在本发明的一个方面，所公开的技术检测先前基于网格编码的信息，并且基于网格对检测到的信息进行解码以提供解码信息。 解码的信息对应于通过在获胜状态结束的网格的获胜路径。 所公开的技术可以识别通过网格的一个或多个备选路径，其也以胜利状态结束，并且可以为每个备选路径生成潜在的错误模式。