公开(公告)号：US5982003A

公开(公告)日：1999-11-09

申请号：US461355

申请日：1995-06-05

申请人： Chenming Hu ,  Mansun John Chan ,  Hsing-Jen Wann ,  Ping Keung Ko

发明人： Chenming Hu ,  Mansun John Chan ,  Hsing-Jen Wann ,  Ping Keung Ko

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L31/0392

CPC分类号： H01L29/42384 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78696 ,  H01L27/1207

摘要： An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

公开(公告)号：US5790436A

公开(公告)日：1998-08-04

申请号：US963510

申请日：1997-11-03

申请人： James Chieh-Tsung Chen ,  Zhihong Liu ,  Chenming Hu ,  Ping Keung Ko

发明人： James Chieh-Tsung Chen ,  Zhihong Liu ,  Chenming Hu ,  Ping Keung Ko

IPC分类号： G06F17/50 ,  H01L21/66 ,  G06F17/00

CPC分类号： H01L22/20 ,  G06F17/5036

摘要： A system and method of simulating operation of an integrated circuit. First, circuit characteristics of circuit components are measured, and a set of circuit simulation model parameters are generated for each measured circuit component. Then, the operation of predefined circuit primitives is simulated using each of the generated sets of circuit simulation model parameters. The circuit primitives include the measured circuit components. The simulated operations are then analyzed to select ones of the simulated operations that are worst, best and nominal with respect to a specified circuit performance parameter and to extract model parameters corresponding to the worst case, best case and nominal case sets of circuit simulation model parameters from the generated sets of circuit simulation model parameters. Each extracted set of circuit simulation model parameters comprises one of the generated sets of circuit simulation model parameters. Then a target circuit is simulated using each of the worst case, best case and nominal case sets of circuit simulation model parameters so as to generate data representing the target circuits under worst case, best case and nominal case manufacturing conditions.

摘要翻译： 一种模拟集成电路运行的系统和方法。 首先测量电路元件的电路特性，并为每个测量的电路元件生成一组电路仿真模型参数。 然后，使用每个生成的电路仿真模型参数集来模拟预定义电路图元的操作。 电路图元包括测量的电路元件。 然后分析模拟操作以选择相对于指定电路性能参数为最差，最佳和标称的模拟操作，并提取对应于电路仿真模型参数的最坏情况，最佳情况和标称情况集的模型参数 从生成的电路模拟模型参数集。 每个提取的电路仿真模型参数集包括生成的电路仿真模型参数集之一。 然后使用电路仿真模型参数的最坏情况，最佳情况和标称情况集合中的每一个模拟目标电路，以便在最坏情况，最佳情况和名义情况制造条件下生成表示目标电路的数据。

公开(公告)号：US6121077A

公开(公告)日：2000-09-19

申请号：US393767

申请日：1999-09-10

申请人： Chenming Hu ,  Mansun John Chan ,  Hsing-Jen Wann ,  Ping Keung Ko

发明人： Chenming Hu ,  Mansun John Chan ,  Hsing-Jen Wann ,  Ping Keung Ko

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/42384 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78696 ,  H01L27/1207

摘要： An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

摘要翻译： 具有改善的电特性的SOI MOSFET包括在源极区域下方的低阻挡体接触，以及在漏极区域下方，以便于收集和去除由冲击电离产生的电流载流子。 完全耗尽和非完全耗尽的SOI MOSFET可以集成在同一芯片上，通过提供一些具有较厚源极和漏极区域的晶体管，其间具有凹陷沟道并且通过选择性沟道掺杂剂注入。 因此，数字电路和模拟电路可以组合在一个基板上。 通过首先去除硅薄膜和下面的绝缘屏障，通过制造直接在支撑衬底中的保护电路的晶体管来提供改进的静电放电保护。 或者，通过在多个电隔离段中制造晶体管，可以在硅膜中形成用于静电放电保护的改进的晶体管，每个段具有由沟道区分开的源极和漏极区域，其中该区域与其它区域中的相似区域电互连 细分。 与较宽的未分段器件的ESD电流相比，可以实现增加的ESD电流。

公开(公告)号：US06300649B1

公开(公告)日：2001-10-09

申请号：US09632456

申请日：2000-08-04

申请人： Chenming Hu ,  Mansun John Chan ,  Hsing-Jen Wann ,  Ping Keung Ko

发明人： Chenming Hu ,  Mansun John Chan ,  Hsing-Jen Wann ,  Ping Keung Ko

IPC分类号： H01L27108

CPC分类号： H01L29/42384 ,  H01L27/1207 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78696

摘要： An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

摘要翻译： 具有改善的电特性的SOI MOSFET包括在源极区域下方的低阻挡体接触，以及在漏极区域下方，以便于收集和去除由冲击电离产生的电流载流子。 完全耗尽和非完全耗尽的SOI MOSFET可以集成在同一芯片上，通过提供一些具有较厚源极和漏极区域的晶体管，其间具有凹陷沟道并且通过选择性沟道掺杂剂注入。 因此，数字电路和模拟电路可以组合在一个基板上。 通过首先去除硅薄膜和下面的绝缘屏障，通过制造直接在支撑衬底中的保护电路的晶体管来提供改进的静电放电保护。 或者，通过在多个电隔离段中制造晶体管，可以在硅膜中形成用于静电放电保护的改进的晶体管，每个段具有由沟道区分隔的源极和漏极区域，其中区域与其它区域中的相似区域电互连 细分。 与较宽的未分段器件的ESD电流相比，可以实现增加的ESD电流。