公开(公告)号：US06501757B1

公开(公告)日：2002-12-31

申请号：US09519072

申请日：2000-03-06

Applicant: Muthusamy Kamaraj ,  Mariamma Joselin ,  Kalyanaraman Pattabhiraman ,  Satish Manohar Kulkarni ,  Jain Philip ,  Jayant Bhatnagar ,  Pradeep Kumar Bhatnagar ,  Kailash Narain Gupta ,  Adde Palli Gopinath Dixit

Inventor： Muthusamy Kamaraj ,  Mariamma Joselin ,  Kalyanaraman Pattabhiraman ,  Satish Manohar Kulkarni ,  Jain Philip ,  Jayant Bhatnagar ,  Pradeep Kumar Bhatnagar ,  Kailash Narain Gupta ,  Adde Palli Gopinath Dixit

IPC: H04L1228

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/309 ,  H04L49/455 ,  H04L49/606 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

Abstract: An ATM switch having a plurality of input-ports and a plurality of output ports allowing a plurality of priority levels, which is highly modular allowing expansion of the number of cell buffers in a shared buffer pool, thus efficiently handling bursty traffic of one-to-one and one-to-many destination ports, using the bit slicing concept to reduce the operating speed of the switch, and decrease the cell buffer size requirement per slice along with reducing the number of shared queue memories per slice, aiding cost effective and efficient, very large scale integration (VLSI) implementation. It also allows configurability of input link speeds, taking care of the order of cell delivery to the output ports. The switch on receiving the input cell, searches for a free buffer in the shared pool, then routes the cell into this buffer and indexes the pointer into an output queue called the queue management module which uses a shared pool of queue memories. The buffers are then read out in the order of priority and sequence of arrival at the input, by this queue management module. It provides initialization, control and status monitoring features too, through a processor interface module.

Abstract translation: 具有多个输入端口和允许多个优先级的多个输出端口的ATM交换机，其高度模块化，允许扩展共享缓冲池中的信元缓冲器的数量，从而有效地处理一到一个的突发业务 - 一个和一对多的目的地端口，使用位分割概念来降低交换机的操作速度，并且减少每个切片的单元缓冲器大小要求，同时减少每个切片的共享队列存储器的数量，有助于成本有效和 高效，大规模集成（VLSI）实现。 它还允许输入链路速度的可配置性，以及小区传输到输出端口的顺序。 接收输入单元的开关在共享池中搜索可用的缓冲区，然后将该单元路由到该缓冲区中，并将该指针编入一个名为队列管理模块的输出队列，该队列使用共享的队列存储池。 然后，通过该队列管理模块以优先顺序到达输入的顺序读出缓冲器。 它还通过处理器接口模块提供初始化，控制和状态监视功能。